Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-12-29
2003-05-13
Coleman, William David (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S616000
Reexamination Certificate
active
06563152
ABSTRACT:
FIELD OF THE INVENTION
A method of obtaining a high mobility channel in a metal-oxide-semiconductor (MOS) transistor is described. More specifically, the present invention describes a method for forming a strain layer on an underside of a channel in the MOS transistor in order to produce a mechanical stress in the channel.
BACKGROUND OF THE INVENTION
A conventional metal-oxide-semiconductor (MOS) transistor generally includes a semiconductor substrate, such as silicon, having a source, a drain, and a channel positioned between the source and drain. A gate stack comprised of a conductive material (a gate conductor), an oxide layer (a gate oxide), and sidewall spacers, is typically located above the channel. The gate oxide is typically located directly above the channel, while the gate conductor, generally comprised of polycrystalline silicon (polysilicon) material, is located above the gate oxide. The sidewall spacers protect the sidewalls of the gate conductor.
Generally, for a given electric field across the channel of an MOS transistor, the amount of current that flows through the channel is directly proportional to a mobility of carriers in the channel. Thus the higher the mobility of the carriers in the channel, the more current can flow and the faster a circuit can perform when using high mobility MOS transistors.
One way to increase the mobility of the carriers in the channel of an MOS transistor is to produce a mechanical stress in the channel. A current method for stressing the channel includes depositing a strain layer on an upper surface of the channel. Using this method, after depositing the strain layer, a gate stack is fabricated and the transistor is realized by implanting dopants into the semiconductor substrate forming a source on one side of the gate stack and a drain of the other side of the gate stack. After the dopants are implanted, a high temperature anneal is required to place the dopants on a crystallographic site in the silicon. A disadvantage of this method is that the high temperature anneal tends to relax the strain in the channel to a lower strain level, usually resulting in dislocations and/or diffusion in the channel crystal, decreasing the desired mechanical stress in the channel. As a result, it is difficult to produce a desirable increase in the mobility of the carriers in the channel using the prior art method.
The present invention addresses some of the shortcomings noted above.
REFERENCES:
patent: 5891793 (1999-04-01), Gardner et al.
patent: 5955745 (1999-09-01), Yamazaki
patent: 6060387 (2000-05-01), Shepela et al.
patent: 6069046 (2000-05-01), Gardner et al.
patent: 6111292 (2000-08-01), Gardner et al.
Sorab K. Ghandhi, “VLSI Fabrication Principles, Silicon and Gallium Arsenide”, John Wiley & Sons, 1st ed, pp. 299-321 and 361.
Doyle Brian S.
Roberds Brian
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
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