Static information storage and retrieval – Read/write circuit – Data refresh
Patent
1985-10-04
1987-12-01
Hecker, Stuart N.
Static information storage and retrieval
Read/write circuit
Data refresh
365194, G11C 700, G11C 1124, G11C 1134
Patent
active
047109025
ABSTRACT:
Memory cells in a dynamic random access memory are coupled to bit lines which are coupled to sense amplifiers. Memory cells are enabled by an enabled word line which causes the memory cells to output data onto the bit lines to which they are coupled. A selected bit line is coupled to a data line while the sense amplifier is amplifying the signal provided by the memory cell. The effect of coupling the bit line to the data line is to hinder the refresh of the selected memory cell because the bit line does not reach full power supply voltage due to the loading by the data line. Full refresh is obtained by keeping the word line enabled for a predetermined time following the bit line being decoupled from the data line so the sense amplifier can bring the bit line to full power supply potential.
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Morton Bruce L.
Pelley III Perry H.
Bowler Alyssa H.
Clingan Jr. James L.
Fisher John A.
Hecker Stuart N.
Motorola Inc.
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