Technique of producing tapered features in integrated circuits

Details Technique of producing tapered features in integrated circuits Technique of producing tapered features in integrated circuits

1982-11-18

1985-04-30

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156646, 156651, 1566591, 1566611, 204192E, B44C 122, C03C 1500, C03C 2506

Patent

active

045142521

ABSTRACT:
A technique is presented for producing tapered walls. In accordance with the disclosed technique, a mask is generated on a workpiece and the workpiece is etched through the mask to replicate the mask pattern into the mask. These steps result in walls at the boundaries of the replicated mask features. In many such processes, these walls are either substantially vertical or have an overhanging portion of the walls. In order to taper the walls, the upper corners of the walls are cut away to remove the overhang or to cut the corner back an additional amount to produce a controlled amount of taper.

REFERENCES:
patent: 3428503 (1969-02-01), Beckerle
patent: 3878008 (1975-04-01), Gleason et al.

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