Electronic digital logic circuitry – Interface – Logic level shifting
Reexamination Certificate
2002-09-10
2004-11-16
Chang, Daniel D. (Department: 2819)
Electronic digital logic circuitry
Interface
Logic level shifting
C326S063000
Reexamination Certificate
active
06819137
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to digital interface circuitry and, more particularly, to a technique for voltage level shifting in input circuitry.
BACKGROUND OF THE INVENTION
As digital circuitry and systems have evolved, they have been designed to utilize steadily lower supply voltage levels. For example, early Transistor-Transistor-Logic (TTL) digital logic circuits typically operated from a 5 volt (V) power supply. As the need for power efficiency has grown, primarily with respect to mobile devices, the typical power supply voltage for devices dropped to 3V, and now devices designed to operate from 1.8V supply levels dominate the market. Also, as the transistor geometries for integrated circuit technology have dropped, some devices are unable to operate using higher voltage supply levels. Further, lower voltage levels reduce output voltage swings and, consequently, the noise produced circuits.
However, many architectural standards, such as bus standards, were developed when a different logical voltage level was the norm. Also, systems may incorporate devices having different supply voltage requirements. For example, a system may include a processor, memory controller, and memory that are designed to operate using 1.8V, while the system bus may be designed to operate using 3.3V. To alleviate this problem, some systems are designed to support several different voltage levels. For example, the Peripheral Control Interface (PCI) local bus is designed to operate using both 5V and 3.3V signaling levels. See the PCI Local Bus Specification version 2.2, which is hereby incorporated by reference herein in its entirety.
FIG. 1
illustrates an example of a system architecture
10
utilizing a PCI local bus
40
. A microprocessor
20
directly interfaces to a cache
22
and memory controller
30
via a processor bus
24
. Memory controller
30
also interfaces to a dynamic random access memory (DRAM) device
32
and to PCI local bus
40
. The memory controller
30
provides a bridge to the PCI bus from the processor bus
24
and handles access to DRAM
32
and to devices coupled to PCI local bus
40
for the processor
20
. System architecture
10
includes a representative selection of peripheral devices such as, for example, a network interface
42
for communications with an external network such as a local area network (LAN), a graphics interface
44
for driving a video output, a peripheral interface
46
for interfacing to other peripheral devices, such as keyboards, modems, etc., and a disk controller
50
for controlling bulk storage to disk
52
.
Today, processor
20
, cache
22
, memory controller
30
, and DRAM
32
are often designed for use with a 1.8V supply. However, as noted above, the PCI standard currently calls for logic signaling levels based on 3.3V or 5V. This raises the problem of interfacing between devices operating using different supply levels.
Systems may incorporate devices operating from a variety of supply sources having different levels.
FIG. 2
is a diagram of a Rambus clock generation architecture
60
, wherein a system clock source
80
operating from voltage supply V
DD
IR (e.g., 3V) produces a reference clock signal REFCLK that is input to a Direct Rambus Clock Generator (DRCG) circuit
70
. The DRCG circuit
70
is operating from another voltage supply V
DD
(e.g., 1.8V) and producing a bus clock signal BUS CLOCK, which is based on a Rambus Signal Level (RSL) using supply voltage V
DD
IPD (e.g., 1.8V), which results in a signal voltage swing between 1.0V and 1.8V. The bus clock signal BUS CLOCK, in turn, drives Rambus DRAMs (RDRAMs) 92-94, which are controlled by memory controller
90
through the use of a termination resistor
62
. See Direct Rambus Clock Generator, Document DL-0056, Version 1.2, Rambus Inc., November 2000, which is hereby incorporated by reference herein in its entirety.
In order to deal with voltage differences between external signal levels (e.g., the bus clock signal BUS CLOCK operating between 1.0V and 1.8V) and internal voltage levels (e.g., the memory controller
90
typically operating below 1.8V), an input level shifter stage is typically used.
FIG. 3
illustrates one example of an input level shifter circuit relating to the clock generation architecture
60
of FIG.
2
. An output pin of clock source
80
includes an output driver
82
that operates from the supply voltage V
DD
IR, which typically ranges from 1.3V to 3.3V. The output signal from output driver
82
reflects the voltage level of V
DD
IR. The output driver
82
drives an input pin of DRCG circuit
70
, which includes an input comparator
72
that operates from supply voltage V
DD
IPD. DRCG circuit
70
also has an input that receives V
DD
IR, which is divided by resistors
74
and
76
to obtain a threshold voltage that is input to comparator
72
. Comparator
72
compares the voltage signal received from output driver
82
with the threshold voltage obtained by dividing V
DD
IR in order to generate a received signal having logic voltage levels that reflect the voltage level V
DD
IPD.
Conventional input level shifters appear in a variety of forms, such as an operational amplifier network, a resistive divider network, or a source follower.
FIG. 3
illustrates an example of a combination resistive divider and operational amplifier, where comparator
72
is implemented as an operational amplifier.
FIG. 4
illustrates an example of a source follower input circuit
100
comprising a transistor
102
, an input resistor
104
, and a source resistor
106
. In source follower circuit
100
, a higher voltage signal received at D
IN
is reflected at the source of transistor
102
, which is coupled to D
out
, while the drain of transistor
102
is coupled to a supply voltage V
DD
I. The magnitude of the voltage being shifted in source follower circuit
100
is determined by the threshold voltage of transistor
102
.
A variety of other conventional level shifter circuits are shown in U.S. Pat. Nos. 6,160,421; 6,097,215; 5,986,472; 5,973,508; 5,867,010; 5,757,712, 5,751,168; 5,663,663; 5,534,798; and 5,534,795, all of which are hereby incorporated by reference herein in their entirety.
Conventional level shifters have a limited ability to shift from an external voltage level to an internal voltage level. Source follower circuits are dependent on the transistor threshold voltage V
t
and tolerate only a narrow range between the external voltage level and the internal supply voltage. Consequently, source follower circuits must be tuned to each particular application and technology, and in general will affect the yield of silicon (product). In addition, source follower circuits do not provide gain for input signals. In resistive divider circuits, the ratio of the resistors must be selected for the relationship between the external and internal voltage sources for the particular application and technology and, as a result, cannot tolerate much variation in the external supply voltage. Also, the introduction of resistance to the receive path will slow the response of the circuit making resistive dividers unsuitable for high speed applications.
Operational amplifier based circuits can be configured to introduce gain to the input signal path. However, the gain of the operational amplifier is determined by the ratio of the feedback resistance to the input resistance for the amplifier. This ratio is fixed and must be designed for a specific ratio of external to internal voltage levels. The resistance also tends to slow the circuit, resulting in poor high speed performance. For a differential input amplifier circuit, since transistors must generally be stacked and use a low internal voltage supply level (e.g., V
DD
less than 2V
t
), the differential pair of the amplifier will typically run out of headroom to operate. In other words, the supply voltage level typically becomes insufficient to accommodate the output swing of the circuit without introducing distortion. For a single-ended input amplifier circuit, the gain offset can become quite l
Kizer Jade
Lau Benedict
Tran Chanh
Wang Yueyong
Chang Daniel D.
Hunton & Williams LLP
Rambus Inc.
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