Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
1999-06-29
2001-05-15
Lee, Eddie C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S778000, C257S686000, C257S724000
Reexamination Certificate
active
06232667
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to chip containing electronic devices and, in particular, to electronic devices containing an assembly of a plurality of electrically connected stacked chips wherein typically a larger top chip of the assembly is electrically connected to a multi-layer ceramic (MLC) cavity substrate and a smaller lower chip or chips of the assembly are enclosed in the cavity of the substrate and to a method of their manufacture.
2. Description of Related Art
Electronic components utilizing integrated circuit chips are used in a number of applications. Controlled Collapse Chip Connection is an interconnect technology developed by IBM as alternative to wire bonding. This technology is generally known as C4 technology or flip chip packaging. Broadly stated, one or more integrated circuit chips are mounted above a single or multi-layer substrate and pads on each chip are electrically connected to corresponding pads on the substrate by a plurality of electrical connections such as solder bumps. The integrated circuit chips may be assembled on the substrate in a solder bump array such as a 10×10 array. The chip containing substrate is then typically electrically connected to another electronic device such as a circuit board by pin connectors with the total package being used in an electronic device such as a computer.
Flip chip packaging is described in U.S. Pat. No. 5,191,404 which patent is hereby incorporated by reference. In general, flip chip joining is desirable for many applications because the footprint or area required to bond the chip to the substrate is equal to the area of the chip itself. Flip chip joining also exploits the use of a relatively small solder bump which typically measures a height of approximately 1 mil to 1.5 mils and a width of approximately 2 to 4 mils to join the pads on the chip to corresponding pads on the substrate. Electrical and mechanical interconnects are formed simultaneously by reflowing the bumps at an elevated temperature. The C4 joining process is self-aligning in that the wetting action of the solder will align the chip's bump pattern to the corresponding substrate pads. This action compensates for chip to substrate misalignment up to several mils which may be incurred during chip placement.
In the joined flip chip package there is necessarily an opening or space between the pad containing surface of the integrated circuit chip and the pad containing surface of the joined substrate resulting from the thickness of the pads on each surface and the solder bump connection between the pads. This open space can not be tolerated because any interference with the solder connections will adversely affect the performance of the package. For example, moisture, the infusion of thermal paste used to increase heat transfer from the chip and the mechanical integrity of the chip due to the possible breaking of the solder bump electrical connections are all serious problems. To solve these problems, the solder bumps of the joined integrated circuit chips and substrate are typically encapsulated totally or a sealant is used around the chip edges to seal the joined opening.
The encapsulation of integrated circuit chips bonded to substrates to improve their reliability is well known. For non C-4 joining, chips wire bonded or tap bonded are typically completely encapsulated in a transfer molded thermoset or thermoplastic polymer. Basically, this process involves melting the polymer in a cavity within the mold. A plunger then rams the molten polymer through an orifice into the mold ventricle. The integrated circuit chip and substrate are bonded to each other using a polymeric adhesive and the package is placed in the mold and the molten polymer forces in and around the package to totally encapsulate the device.
Flip chip bonding offers many advantages in electronics manufacture compared to the complete encapsulation techniques above and one of the most important is the ability to remove and replace the chip without scrapping the substrate. This removal of the chip by heating and lifting of the chip from the substrate and replacement with typically a new chip is termed rework and can be performed numerous times without degrading the quality or reliability of the reworked electronic component.
Encapsulation of the flip chip packages however presents rework and other problems. The flip chip package must also be reliable and thermal mismatches between the encapsulant, chip, substrate and/or solder bumps must be minimized to avoid stressing and damaging of the package. The encapsulant must also be able to be heated and softened for the lift-off procedure.
Recent developments in electronic component fabrication now provide components utilizing an assembly of stacked chips, instead of a single chip, mounted to a substrate. In general, a plurality of chips are C-4 bonded in a stack assembly resulting in corresponding spaces between each of the bonded chips. Typically, the chips are of about the same size (width and length and surface area) and are mounted to a top chip having a larger width and length and surface area which larger chip has peripheral non-bonded pads and forms the top of the stacked assembly. Once the chips are joined in the assembly, the peripheral non-bonded pads of the top chip of the stacked assembly are then C4 joined to an MLC substrate. This substrate has a cavity to accommodate the smaller connected stacked chips and the uppermost top stacked chip overlies the periphery of the cavity. The peripheral non-bonded C4 bumps on the top chip are then C4 bonded to the surface of the substrate with the smaller stacked chips being positioned and enclosed in the cavity.
The conventional chip underfill process to encapsulate the space between a single chip bonded to a non-cavity substrate surface typically positions the bonded chip above the top of the substrate and then applies the underfill material to the substrate adjacent to the periphery of the chip to be underfilled. Capillary action draws the underfill encapsulated material into the space between the chip and the substrate to form a void free filled space between the chip and the substrate. This technique works very well for a single chip attached to the surface of a substrate but is not reliable for stacked chip assemblies wherein the stacked chips are enclosed in a cavity of a substrate.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a stacked integrated circuit chip assembly comprising a plurality of electrically connected chips with the chip assembly being electrically connected to an interconnection substrate forming an electronic package wherein peripheral non-bonded pads on the uppermost top chip of the assembly are electrically connected to pads on the interconnection substrate with the stacked lower chip or chips of the assembly being enclosed in a cavity in the interconnection substrate with the solder connections between the stacked chips and cavity area being effectively sealed (encapsulated) to provide mechanical, electrical and chemical reliability for the electronic package.
It is another object of the present invention to provide a method for making an electronic component comprising a stacked integrated circuit chip assembly comprising a plurality of electrically connected chips electrically connected to a substrate, the component package having enhanced electrical, mechanical and chemical reliability properties wherein non-electrically connected peripheral pads on the top uppermost stacked chip of the assembly are electrically connected to pads on the surface of the interconnection substrate by solder connections with the lower chip or chips of the assembly being enclosed in a cavity in the substrate and the solder connections between the stacked chips and the cavity encapsulated with an encapsulant.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
Hultmark Eric B.
Noble Brian C.
Ahsan Aziz M.
Cruz Lourdes
DeLio & Peterson LLC
International Business Machines - Corporation
Lee Eddie C.
LandOfFree
Technique for underfilling stacked chips on a cavity MLC module does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Technique for underfilling stacked chips on a cavity MLC module, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Technique for underfilling stacked chips on a cavity MLC module will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2534174