Static information storage and retrieval – Read/write circuit – Testing
Patent
1999-04-30
2000-08-29
Nelms, David
Static information storage and retrieval
Read/write circuit
Testing
365200, 371 251, 371 211, G11C 2900
Patent
active
06111801&
ABSTRACT:
A technique for testing wordline and related circuitry of a memory array is disclosed. The memory array includes a plurality of memory cells arranged in a plurality of rows, wherein each of the plurality of rows has a respective wordline connected to respective ones of the plurality of memory cells. The related circuitry includes a decode circuit connected to each of the respective wordlines for activating at least one of the respective wordlines based upon a corresponding address signal that is decoded by the decode circuit. The technique involves applying an address signal to the decode circuit so as to activate a corresponding one of the respective wordlines, and then monitoring the corresponding one of the respective wordlines so as to determine if the corresponding one of the respective wordlines has been activated and thereby determine if the memory array and related circuitry are operating in a proper manner.
REFERENCES:
patent: 5553082 (1996-09-01), Connor et al.
patent: 5936900 (1999-08-01), Kii et al.
patent: 5995429 (1999-11-01), Kojima et al.
patent: 6002623 (1999-12-01), Stave et al.
Galanthay Theodore E.
Jorgenson Lisa K.
Nelms David
STMicroelectronics Inc.
Szuwalski Andre
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