Technique for sorting high frequency integrated circuits

Details Technique for sorting high frequency integrated circuits Technique for sorting high frequency integrated circuits

1996-07-22

1998-08-18

Nguyen, Hoa T.

Excavating

371 28, G01R 3100, H04B 1700

Patent

active

057967512

ABSTRACT:
A system and method is providing for sorting integrated circuits based upon their maximum operating frequency. More particularly, the incremental time required for a test signal to be flushed through a level sensitive scan design (LSSD) circuit is measured. The test method of the present invention measures scan flush delay in the integrated circuit in order to measure the frequency of the circuit. A free running reference clock and on-chip counter are used measure the flush delay time period. With this information a count/second parameter can be determined, indicating the speed at which the test bit is flushed through the scan chain. The lower the value of the parameter, the higher the operating frequency of the chip.

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