Technique for reducing breakage of thinned flip-chip...

Details Technique for reducing breakage of thinned flip-chip... Technique for reducing breakage of thinned flip-chip...

1999-03-18

2001-11-20

Meier, Stephen D. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Flip chip

Reexamination Certificate

active

06320266

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to multi-layer integrated circuit (IC) devices, and more particularly to reducing breakage risk of thinned multi-layer ICs for device deprocessing.
BACKGROUND OF THE INVENTION
For flip-chip, multi-layer IC devices, debugging for defects in the IC is difficult due to having to approach the desired layers from the backside of the device.
FIG. 1
illustrates a sideview block diagram of a typical flip-chip configuration. As shown in
FIG. 1
, an IC device
10
is coupled to a ceramic package
12
(e.g., a C
4
package) via solder bumps
14
. The solder bumps
14
act as chip-to-carrier interconnects to attach the IC device
10
to the ceramic package
12
and to mate with corresponding pad patterns to form the necessary electrical contacts between the circuit(s) of the IC device
10
and pins of the package
12
.
Device analysis remains a challenge due to the upside-down nature of the flip-chip orientation. Thus, device deprocessing of flip-chip oriented IC devices faces several difficulties. Normal deprocessing utilizes mechanical polishing of the thick silicon backside layer in order to more readily access the circuit features at the frontside layers. The mechanical polishing used from the backside removes the silicon and creates a very thin device. The reduced thickness allows utilization of an infrared (IR) optical device to view the device. A support structure typically holds the device during the thinning process. Once thinned, the device then requires removal from the support before the deprocessing procedure continues. Unfortunately, the thin device created by polishing is difficult to handle and subsequently utilize in further device analysis, which normally requires multiple steps for the removal of the device from the support to perform well-established delayering techniques from a frontside of the device. Breakage of the device often occurs due to the thinness of the device and brittleness of the silicon. Thus, the process is highly problematic and significantly time-consuming.
Accordingly, a need exists for a technique that reduces the risk of breakage when handling thinned dies. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides aspects for supporting thinning of a flip-chip device with reduced risk of breakage. An exemplary apparatus aspect includes a multi-layer integrated circuit device oriented in a flip-chip orientation, and a support substrate transparent to a light source of a predetermined wavelength. The apparatus further includes an adhesive, the adhesive affixing the multi-layer integrated circuit device to the support structure during thinning of the multi-layer integrated circuit device from a backside and sufficiently releasing the multi-layer integrated circuit device when exposed to the light source of the predetermined wavelength through the support substrate after thinning is completed to reduce breakage risk for the thinned multi-layer integrated circuit device.
Through the present invention, less risk of breakage of thinned flip-chip devices is efficiently achieved. The straightforward and innovative utilization of a light-sensitive adhesive and corresponding transparent support structure successfully avoids problems associated with typical device removal techniques. These and other advantages of the aspects of the present invention will be more fully understood in conjunction with the following detailed description and accompanying drawings.


REFERENCES:
patent: 5476566 (1995-12-01), Casavin
patent: 5607099 (1997-03-01), Yeh et al.
patent: 5872365 (1999-02-01), Goh et al.
patent: 6168960 (2001-01-01), Li
Lasers Society 8th Annual Meeting, vol. 1, IEEE, vol. 2 1995, “A room temperature Flip-Chip Mounting Technique for Laser Diodes on Si Motherboard”.

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