Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
Reexamination Certificate
2008-07-08
2008-07-08
Dollinger, Tonia L M (Department: 2181)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Scoreboarding, reservation station, or aliasing
C712S023000
Reexamination Certificate
active
07398375
ABSTRACT:
The present invention provides a dynamic scheduling scheme that uses reservation stations having at least one station that stores an at least two operand instruction. An allocator portion determines that the instruction, entering the pipeline, has one ready operand and one not-ready operand, and accordingly places it in a station having only one comparator. The one comparator then compares the not-ready operand with tags broadcasted on a result tag bus to determine when the not-ready operand becomes ready. Once ready, execution is requested to the corresponding functional unit.
REFERENCES:
patent: 5404470 (1995-04-01), Miyake
patent: 5473526 (1995-12-01), Svensson et al.
patent: 5506520 (1996-04-01), Frank et al.
patent: 5517145 (1996-05-01), Frank
patent: 5526319 (1996-06-01), Dennard et al.
patent: 5546597 (1996-08-01), Martell et al.
patent: 5559478 (1996-09-01), Athas et al.
patent: 5590352 (1996-12-01), Zuraski, Jr. et al.
patent: 5604912 (1997-02-01), Iadonato et al.
patent: 5634026 (1997-05-01), Heaslip et al.
patent: 5655096 (1997-08-01), Branigin
patent: 5838203 (1998-11-01), Stamoulis et al.
patent: RE37552 (2002-02-01), Svensson et al.
patent: 6516405 (2003-02-01), Yoaz et al.
Daniele Folegnani and Antonio Gonzalez, “Energy-Effective Issue Logic”, Proceedings of the 28th Annual International Symposium on Computer Architecture, Jun. 2001. p. 236.
On Pipelining Dynamic Instruction Scheduling Logic by Jared Stark, Mary D. Brown and Yale N. Patt, Microprocessor Research Labs—Intel Corporation and Department of Electrical and Computer Engineering—The University of Texas at Austin.
Efficient Dynamic Scheduling Through Tag Elimination by Dan Ernst & Todd Austin, Advanced Computer Architecture Laboratory—University of Michigan; 29th Annual International Symposium on Computer Architecture, 2002 ISCA.
Low-Power Digital Systems Based on Adiabatic-Switching Principles by William C. Athas, Lars “J.” Svensson, Member IEEE, Jeffrey G. Koller, Nestoras Tzartzanis, and Eric Ying-Chin Chou, Student Member, IEEE in the IEEE Transaction On Very Large Scale Integration (VLSI) Systems, vol. 2, No. 4, Dec. 1994.
A Resonant Clock Generator for Single-Phase Adiabatic Systems by Conrad H. Ziesler, Suhwan Kim and Marios C. Papaefthymiou. P)ublished ISLPED '01, Aug. 6-7, 2001.
Energy Recovering Static Memory by Joohee Kim, Conrad H. Ziesler & Marios C. Papaefthymiou. Published ISLPED '02, Aug. 12-14, 2002.
Austin Todd M.
Ernst Daniel J.
Dollinger Tonia L M
Rader & Fishman & Grauer, PLLC
The Regents of the University of Michigan
LandOfFree
Technique for reduced-tag dynamic scheduling and reduced-tag... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Technique for reduced-tag dynamic scheduling and reduced-tag..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Technique for reduced-tag dynamic scheduling and reduced-tag... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2814159