Technique for low-temperature formation of excellent...

Details Technique for low-temperature formation of excellent... Technique for low-temperature formation of excellent...

1998-12-16

2001-07-03

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S584000

Reexamination Certificate

active

06255203

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a novel process for the fabrication of gate structure, and more particularly to a process suppressing the impurity diffusion through low temperature grown silicided A-Si gate and preventing the gate oxide from impurity penetration.
BACKGROUND OF THE INVENTION
CMOSFET, which consists n-type and p-type metal-oxide-semiconductor field effect transistors, is the essential component in the integrated circuit. As the size of the devices shrinks, it is required to replace the n-type polysilicon gate with its p-type conterpart in order to create surface channel on the p-type MOSFET. The replacement can reduce both the short channel effect and hot carrier effect. In practice, BF
2
+
is implanted to form p-type polysilicon gate and source/drain shallow junction. Unfortunately, fluorine speeds up the diffusion of boron ions in the gate oxide. Consequently, the boron ions reach the silicon substrate and the electric properties and the reliability of the device are deteriorated. For examples, the breakdown field and the charge to breakdown can get smaller and the charge trapping rate of the gate oxide can be increased.
According to the report in IEEE Electron Device Lett. Volume EdL-14, page 179, by G. W. Yoon etc., nitrogen in the gate oxide can stop the penetration of boron ions and is therefore used in the growth of gate oxide. In addition, according to the report in IEEE Electron Device Lett. Volume 15, page 109, U.S. patent application Ser. No. 179,016 and Ser. No. 336,970 by Z. J. Ma etc., NH
3
is used during the anneal process of the gate oxide. The electric properties of the gate oxide by the process deteriorate while the reliability of the gate oxide by the process also deteriorates due to the incorporation of the hydrogen. Moreover, according to the report in IEEE Trans. Electron Devices Volume 42, page 1503 by C. Y. Lin, stacked p-type polysilicon (or silicon) gate structure increases the sheet resistance which is harmful to the operation of high speed devices.
SUMMARY OF THE INVENTION
In accordance with the present invention, a novel process forms silicide at low temperature while the underlying-Si gate remain amorphous. The silicide can be used as implantation barrier to narrow the implantation profile in the gate. During high temperature anneal process, the silicide can serve as an impurity diffusion source. Because the amorphous silicon can retard the impurity diffusion more efficiently than the polysilicon, the impurity can hardly penetrate the gate oxide to reach the silicon substrate. The integrity of the gate oxide is maintained. By the way, amorphous silicon forms smoother interface than polysilicon. Due to the properties mentioned above, the breakdown field and the charge to breakdown can increase. The properties and the reliability of the devices can thus be improved. As the thickness of the gate shrinks, the process in the present invention can provide more tolerance.
Important technical advantage of the present invention is that the present invention can be applied on both n-type and p-type gate structures, especially on the p-type gate structure. It is known that the diffusion rate of the boron ion in the gate is fast and it is even faster when fluorine is present in the gate oxide. The electrical properties and the reliability of the p-type gate can therefore be deteriorated. The present invention can retard the diffusion of the boron so that the properties of the p-gate is reserved.
Other important technical advantages are readily apparent to one skilled in the art from the following figures, descriptions, and claims.


REFERENCES:
patent: 4282647 (1981-08-01), Richman
patent: 5624867 (1997-04-01), Cheng et al.
patent: 6008111 (1999-12-01), Fushida et al.
patent: 6057185 (2000-05-01), Suenaga

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