Electronic digital logic circuitry – Interface – Logic level shifting
Reexamination Certificate
2002-08-12
2004-05-11
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Interface
Logic level shifting
C326S062000, C326S083000, C327S333000, C327S371000
Reexamination Certificate
active
06734705
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to electronic systems and in particular it relates to low voltage to high voltage level shifters.
BACKGROUND OF THE INVENTION
The design of a low voltage to high voltage level shifter usually involves striking a balance between the strength of the pull-down NMOS transistors
20
and
22
and the cross gate-connected PMOS transistors
24
and
26
as shown in the prior art circuit of FIG.
1
. The circuit of
FIG. 1
also includes inverters
28
and
30
; input IN; low voltage source VL; high voltage source VH; outputs OUT and OUT_B; and ground node gnd. If the gains of the NMOS transistors
20
and
22
, and PMOS transistors
24
and
26
are similar, there is the risk of the level shifter not switching output states. If the NMOS transistors
20
and
22
are much stronger than the PMOS transistors
24
and
26
, then the propagation delay of the rising edge of the outputs OUT and OUT_B can be much longer than in the falling edge, due to the weak PMOS transistors. This can be a problem in certain applications, when both rising and falling propagation delays are significant factors.
SUMMARY OF THE INVENTION
A low voltage to high voltage level shifter has falling-edge 1-shot circuits coupled to the outputs of a basic level shifter with cross gate-connected transistors and two pull-down transistors. The falling-edge 1-shot circuits output a narrow pulse when these outputs transition from a high state to a low state. These pulses are used to set and reset a flip-flop. The flip flop provides an output that is only dependent on the very fast fall times of the outputs of the basic level shifter. This allows the level shifter to be designed for optimal transitional performance without the sacrifice of a potentially long propagation delay on the output nodes.
REFERENCES:
patent: 5896043 (1999-04-01), Kumagai
patent: 6373315 (2002-04-01), Tsuji et al.
Briggs David D.
Pulkin Mark
Stewart Alan K.
Tan Vibol
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