Technique for improving bonding strength of leadframe to substra

Details Technique for improving bonding strength of leadframe to substra Technique for improving bonding strength of leadframe to substra

1995-11-07

1997-08-26

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With structure for mounting semiconductor chip to lead frame

257692, 257774, 361774, 361813, 361820, H01L 23495, H01L 2348

Patent

active

056613377

ABSTRACT:
A semiconductor substrate layer is provided which includes a plurality of severed through holes (or metallized half vias) along an edge portion of the substrate layer. The bonding fingers of a leadframe are then formed into a down set (or up set) format and soldered to the substrate at the severed, plated through holes. This technique increases the contact area between the leadframe and the substrate. In addition, the down set (or up set) format of the leadframe bonding fingers decreases the stress built up due to CTE mismatch between the substrate and the leadframe.

REFERENCES:
patent: 5247423 (1993-09-01), Lin et al.
patent: 5293066 (1994-03-01), Tsumura
patent: 5394298 (1995-02-01), Sagisaka
patent: 5434745 (1995-07-01), Shokrgozar et al.

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