Technique for generating input stimulus to cover properties...

Details Technique for generating input stimulus to cover properties... Technique for generating input stimulus to cover properties...

2006-02-13

2008-11-18

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07454726

ABSTRACT:
A design of an integrated circuit is first verified using directed and/or random test cases. For a cover directive not covered by the directed and/or random test cases, a property is created, where a simulation trace that causes the property to fail covers the cover directive. Thereafter, the property is evaluated, and dependent on the evaluation, the simulation trace is dumped and stored for subsequent exercising of the cover directive.

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patent: 7007251 (2006-02-01), Hekmatpour
patent: 7203882 (2007-04-01), Fine et al.
patent: 7278056 (2007-10-01), Hekmatpour

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