Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2008-09-09
2008-09-09
Tran, Long K (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S600000, C257SE21521, C257SE21524, C257SE21525, C438S011000, C438S014000, C438S018000, C700S121000, C700S108000
Reexamination Certificate
active
11738219
ABSTRACT:
The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter of the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.
REFERENCES:
patent: 6859031 (2005-02-01), Pakdaman et al.
patent: 7220990 (2007-05-01), Aghababazadeh et al.
patent: 2005/0085032 (2005-04-01), Aghababazadeh et al.
patent: 2005/0085932 (2005-04-01), Aghababazadeh et al.
patent: 2005/0090027 (2005-04-01), Aghababazadeh et al.
patent: 2005/0090916 (2005-04-01), Aghababazadeh et al.
patent: 2007/0004063 (2007-01-01), Aghababazadeh et al.
U.S. Appl. No. 10/927,258, Aghababazadeh et al.
U.S. Appl. No. 10/927,260, Aghababazadeh et al.
U.S. Appl. No. 10/927,275, Aghababazadeh et al.
U.S. Appl. No. 10/927,406, Aghababazadeh et al.
U.S. Appl. No. 11/469,305, Aghababazadeh et al.
U.S. Appl. No. 11/762,944, Aghababazadeh et al.
U.S. Appl. No. 11/763,001, Aghababazadeh et al.
USPTO Notice of Allowance dated Mar. 21, 2007 in U.S. Appl. No. 10/927,258, published as US 2005-0090027 A1, 14 pages.
USPTO Notice of Allowance dated Jan. 25, 2007 in U.S. Appl. No. 10/927,260, issued as patent No. 7,220,990 B2, 12 pages.
USPTO Notice of Allowance dated Mar. 17, 2006 in U.S. Appl. No. 10/927,260, issued as patent No. 7,220,990 B2, 8 pages.
USPTO Office Action dated Jun. 20, 2007 in U.S. Appl. No. 10/927,275, published as US 2005-0085392 A1, 4 pages.
USPTO Office Action dated Sep. 25, 2006 in U.S. Appl. No. 10/927,258, published as US 2005-0090027 A1, 6 pages.
USPTO Office Action dated Mar. 28, 2007 in U.S. Appl. No. 10/927,406, published as US 2005-0090916 A1, 6 pages.
USPTO Office Action dated Jul. 3, 2006 in U.S. Appl. No. 10/927,406, published as US 2005-0090916 A1, 6 pages.
USPTO Office Action dated Sep. 27, 2005 in U.S. Appl. No. 10/927,260, issued as patent No. 7,220,990 B2, 5 pages.
Aghababazadeh Majid
Estabil Jose J.
Pakdaman Nader
Steinbrueck Gary L.
Vickers James S.
Shemwell Mahamedi LLP
tau-Metrix, Inc.
Tran Long K
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