Technique for elimination of pitting on silicon substrate during

Details Technique for elimination of pitting on silicon substrate during Technique for elimination of pitting on silicon substrate during

1996-07-16

2000-07-11

Niebling, John F.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438660, 438683, 438592, H01L 213205, H01L 2144

Patent

active

060872543

ABSTRACT:
A method for forming a gate stack which minimizes or eliminates damage to the gate dielectric layer and/or silicon substrate during the gate stack formation by the reduction of the temperature during formation. The temperature reduction prevents the formation of silicon clusters within the metallic silicide film in the gate stack which has been found to cause damage during the gate etch step. The present invention also includes methods for dispersing silicon clusters prior to the gate etch step.

REFERENCES:
patent: 5103272 (1992-04-01), Nishiyama
patent: 5183782 (1993-02-01), Onishi et al.
patent: 5268330 (1993-12-01), Givens et al.
patent: 5320975 (1994-06-01), Cederbaum et al.
patent: 5322806 (1994-06-01), Kohno et al.
patent: 5428244 (1995-06-01), Segawa et al.
patent: 5438006 (1995-08-01), Chang et al.
patent: 5492597 (1996-02-01), Keller
patent: 5512502 (1996-04-01), Ootsuka et al.
patent: 5518942 (1996-05-01), Shrivastava
patent: 5518958 (1996-05-01), Giewont et al.
patent: 5656546 (1997-08-01), Chen et al.
patent: 5665646 (1997-09-01), Kitano
patent: 5728625 (1998-03-01), Tung

Affiliated with

Also associated with

Rating

Technique for elimination of pitting on silicon substrate during does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Technique for elimination of pitting on silicon substrate during, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Technique for elimination of pitting on silicon substrate during will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-541897