Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2006-10-03
2006-10-03
Weiss, Howard (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
Reexamination Certificate
active
07115492
ABSTRACT:
A method for forming a gate stack which minimizes or eliminates damage to the gate dielectric layer and/or silicon substrate during the gate stack formation by the reduction of the temperature during formation. The temperature reduction prevents the formation of silicon clusters within the metallic silicide film in the gate stack which has been found to cause damage during the gate etch step. The present invention also includes methods for dispersing silicon clusters prior to the gate etch step.
REFERENCES:
patent: 4443930 (1984-04-01), Hwang et al.
patent: 4704783 (1987-11-01), Possin et al.
patent: 4755480 (1988-07-01), Yau et al.
patent: 4782037 (1988-11-01), Tomozawa et al.
patent: 5006421 (1991-04-01), Yang et al.
patent: 5103272 (1992-04-01), Nishiyama
patent: 5183782 (1993-02-01), Onishi et al.
patent: 5268330 (1993-12-01), Givens et al.
patent: 5320975 (1994-06-01), Cederbaum et al.
patent: 5322806 (1994-06-01), Kohno et al.
patent: 5428244 (1995-06-01), Segawa et al.
patent: 5438006 (1995-08-01), Chang et al.
patent: 5472896 (1995-12-01), Chen et al.
patent: 5492597 (1996-02-01), Keller
patent: 5512502 (1996-04-01), Ootsuka et al.
patent: 5518942 (1996-05-01), Shrivastava
patent: 5518958 (1996-05-01), Giewont et al.
patent: 5656546 (1997-08-01), Chen et al.
patent: 5665646 (1997-09-01), Kitano
patent: 5728625 (1998-03-01), Tung
patent: 6087254 (2000-07-01), Pan et al.
patent: 6137130 (2000-10-01), Sung et al.
patent: 6465295 (2002-10-01), Kitamura
patent: 0591086 (1994-04-01), None
Iyer Ravi
Liu Louie
Pan Pai-Hung
Micro)n Technology, Inc.
TraskBritt
Weiss Howard
LandOfFree
Technique for elimination of pitting on silicon substrate... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Technique for elimination of pitting on silicon substrate..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Technique for elimination of pitting on silicon substrate... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3709272