Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
Patent
1998-09-24
2000-10-31
De Cady, Albert
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error/fault detection technique
714 5, 714767, H03M 1300
Patent
active
061417890
ABSTRACT:
The bits of a data block are logically partitioned into an array that includes a number of columns equal to a number of memory devices and a number of rows equal to a number of bits of the data block stored in each memory device. Each memory device contributes one bit to each row. In one embodiment, the bits from a memory device are stored in the same column position of all the rows. One check bit is associated with each row. The check bit is computed by taking the parity of the row associated with the check bit and zero or one column. Each column is assigned to at least four check bits. If a check bit has a column assigned to it, then the check bit is generated by computing the parity of the associated row and the column assigned to the check bit. Alternatively, if the check bit does not have a column assigned to it, the check bit is generated by computing the parity of the row assigned to the check bit only. Each column is assigned to at least four check bits and is assigned to an even number of check bits.
REFERENCES:
patent: 4589112 (1986-05-01), Karim
patent: 4995041 (1991-02-01), Hetherington et al.
patent: 5164944 (1992-11-01), Benton et al.
patent: 5612965 (1997-03-01), Michaelson
patent: 5666371 (1997-09-01), Purdham
patent: 5909541 (1999-06-01), Sampson et al.
patent: 6035432 (2000-03-01), Jeddeloh
"32-Bit-Wide Memory Tolerates Failures," NTIS Tech Notes, Oct. 1990, p. 818.
International Search Report, Application No. PCT/US99/22024, mailed Jan. 21, 2000.
Dell, "A White Paper on the Benefits of Chipkill-Correct ECC for PC Server Main Memory," IBM Microelectronics Division, Nov. 1997, pp. 1-23.
"Parallel Parity," http://bbs-koi.uniinc.msk.ru/tech1/1994/er.sub.-- cont/block.htm, 1994, 1 pg.
"Modulo-2 Arithmetic," http://bbs-koi.uniinc.msk.ru/tech1/1994/er.sub.-- cont/modulo.htm, 1994, 1 pg.
"Introduction to Error Control," http://bbs-koi.uniinc.msk.ru/tech1/1994/er.sub.-- cont/intro.htm, 1994, 1 p.
Barker et al. "ASCII Table," http://www.eng2.uconn.edu/cse/Cour...08W/References/Ref.sub.-- ASCIITable.html, Feb. 1998, 1 pg.
"Parity & Computing parity," http://bbs-koi.uniinc.msk.ru/tech1/1994/er.sub.--- cont/parity.htm, 1994, 2 pgs.
"Error Correction with Hamming Codes," http://bbs-koi.uniinc.msk.ru/tech1/1994/er.sub.-- cont/hamming.htm, 1994, 2 pgs.
Barker et al. "Hamming Code, Background Information," http://www.eng2.uconn.edu/cse/Courses/CSE208W/Hamming/Background.html, Feb. 1998, 3 pgs.
Barker et al., "Hamming Code, Theory," http://www.eng2.uconn.edu/cse/Courses/CSE208W/Hamming/Theory.html, Mar. 1998, 2 pgs.
"NUMA: Delivering the Next Level of Commodity SMP Performance," http://199.245.235.23
ewsletters/html/vpoint5.html, 1996, 4 pgs.
Barker et al. "Generation Definitions," http://www.eng2.uconn.edu/cse/Cour...8W/References/Ref.sub.-- Definitions.html, Feb. 1998, 3 pgs.
Barker et al. "Hamming Code, Lab Procedure," http://www.eng2.uconn.edu/cse/Courses/CSE208W/Hamming/Procedure.html, Jun. 1998, 3 pgs.
Abraham Esaw
Cady Albert De
Kivlin B. Noel
Sun Microsystems Inc.
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