Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2005-04-14
2008-10-21
Chambliss, Alonzo (Department: 2892)
Semiconductor device manufacturing: process
With measuring or testing
C438S018000, C438S401000, C257S048000, C257S772000, C257S797000, C257SE21529
Reexamination Certificate
active
07439083
ABSTRACT:
Substrate shrinkage that occurs during manufacture of an electronic assembly is compensated for by the incorporation of a horizontal line, having a plurality of vertical graduations, across a horizontal portion of a substrate and a vertical line, having a plurality of horizontal graduations, across a vertical portion of the substrate. The substrate is then cured and an amount of substrate shrinkage is determined, based upon a location change in the graduations of the horizontal and vertical lines. In this manner, solder can be properly provided on solder pads of the substrate responsive to the amount of substrate shrinkage. As such, electronic components can be properly mounted to the solder pads of the substrate.
REFERENCES:
patent: 5162240 (1992-11-01), Saitou et al.
patent: 5385289 (1995-01-01), Bloch et al.
patent: 6635549 (2003-10-01), Kyoh et al.
patent: 6963389 (2005-11-01), Fukada
patent: 2001/0049589 (2001-12-01), Yasuda et al.
patent: 3305325 (1984-05-01), None
patent: 0239326 (2002-05-01), None
EP Search Report dated Jul. 6, 2007.
Badgett Jerome L.
Fairchild M. Ray
Chambliss Alonzo
Delphi Technologies Inc.
Funke Jimmy L.
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