Technique for automated alignment of semiconductor chips

Details Technique for automated alignment of semiconductor chips Technique for automated alignment of semiconductor chips

1997-12-03

2000-02-08

Font, Frank G.

Optics: measuring and testing

By alignment in lateral direction

G01B 1100

Patent

active

060233362

ABSTRACT:
A method and apparatus for accurate automated alignment of semiconductor chips (12,14) or thin-film networks includes forming a plurality of vias (16-19,22-25) in each integrated circuit element in respective locations, and moving the integrated circuit elements to bring the corresponding vias into alignment. In one embodiment, the integrated circuit elements (12,14) are moved by inserting a plurality of spindles (36-39) into respective vias in the integrated circuit elements to align the integrated circuit elements. In another embodiment, the integrated circuit elements (40,42) are moved by providing a source of light (48) on one side of the integrated circuit elements and a light sensor (50) on another side of the integrated circuit elements, and moving the integrated circuit elements to maximize the amount of light traversing the vias (44,46). To enable precision alignment of the integrated circuit elements, the vias may be formed with diameter less than 50 .mu.m.

REFERENCES:
patent: 4253079 (1981-02-01), Brosh
patent: 4286201 (1981-08-01), Roecks et al.

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