Television – Bandwidth reduction system – Data rate reduction
Patent
1993-05-26
1997-11-04
Chin, Tommy P.
Television
Bandwidth reduction system
Data rate reduction
342402, 342405, 342413, 342416, H04N 732
Patent
active
056845340
ABSTRACT:
A video processor system has separate and independent video processors for performing a variety of video processor functions required for encoding and decoding video signals. Each of the separate video processors performs its own individual set of video processor functions. During the encode process the first video processor performs motion estimation to provide motion estimation information which it applies to the second video processor. The second video processor receives the motion estimation information and performs forward and inverse discrete cosine transforms, quantization and dequantization, frame addition and frame differencing, as well as run length encoding. The run length encoding operation produces run/value pairs which are then applied to the first video processor. The first video processor performs variable length encoding upon the run/value pairs. During the decoding process the first video processor performs a variable length decode and applies the variable length decoded data to the second video processor. The second video processor performs run length decoding, dequantization, inverse discrete cosine transforms and frame addition according to the received variable length data. The inverse transformed data produced by this operation is then applied to the first video processor.
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Harney Kevin
Kelly Mike S.
Loeser Gary
Chin Tommy P.
Intel Corporation
Kinsella N. Stephen
Le Vu
Murray William H.
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