Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-06-19
2007-06-19
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
09935789
ABSTRACT:
A system and method of designing digital system. One aspect of the invention includes a method for designing an essentially digital system, wherein Pareto-based task concurrency optimization is performed. The method uses a system-level description of the functionality and timing of the digital system. The system-level description comprises a plurality of tasks. Task concurrency optimization is performed on said system-level description, thereby obtaining a task concurrency optimized system-level description, including Pareto-like task optimization information. The essentially digital system is designed based on said task concurrency optimized system-level description. In one embodiment of the invention, the description is includes a “grey-box” description of the essentially digital system.
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Catthoor Francky
Cossement Nathalie
Lauwereins Rudy
Marchal Paul
Prayati Aggeliki
Garbowski Leigh M.
Interuniversitair Microelektronica Centrum
Katholieke Universiteit Leuven
Patras, University of
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