Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
1999-06-11
2002-09-24
Lefkowitz, Sumati (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C370S351000, C370S431000, C370S464000
Reexamination Certificate
active
06457084
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to computer systems and more particularly to a computer system having a high speed communication link with multiple channels operating on the communication link.
2. Description of the Related Art
Traditional personal computer architectures partition the computer system into the various blocks shown in the exemplary prior art system illustrated in FIG.
1
. One central feature of this prior art architecture is the use of the Peripheral Component Interface (PCI) bus
101
as the connection between the “north bridge” integrated circuit
103
and the “south bridge” integrated circuit
105
. The north bridge functions generally as a switch connecting CPU
107
, a graphics bus
109
such as the Advanced Graphics Port (AGP) bus, the PCI bus and main memory
111
. The north bridge also contains the memory controller function.
The south bridge generally provides the interface to the input/output (I/O) portion of the system with the possible exception of video output as illustrated in FIG.
1
. Specifically, the south bridge
105
provides a bridge between the PCI bus and legacy PC-AT (Advanced Technology) logic. The south bridge also provides a bridge to the legacy ISA bus
115
, the Integrated Device Electronics (IDE) disk interface
117
and the Universal Serial Bus (USB)
119
. In the illustrated prior art architecture, PCI bus
101
also functions as the major input/output bus for add-in functions such as network connection
121
. The various busses and devices shown in
FIG. 1
are conventional in the personal computer industry and are not described further herein unless necessary for an understanding of the present invention.
In current and future personal computer systems, two basic types of data are transferred between integrated circuits: isochronous data and asynchronous data. Isochronous data refers to data used in real-time data streams such as audio data or motion-picture video data. Asynchronous data is used for all other transfers, such as central processing unit (CPU) accesses to memory and peripherals or bulk data transmissions from a hard drive into system memory.
The PCI bus causes a lack of determinism in the system because any function on the PCI bus can become master of the bus and tie up the bus. Thus, the throughput available on the PCI bus for a particular transfer and the latency that is involved for that transfer is unknown. PCI bus load fluctuations can result in uncertain and irregular quality of service. Therefore, having a PCI bus as the major input/output bus means that the major input/output bus of present day computer systems does not provide proper support for both isochronous and asynchronous data. If a computer system gives asynchronous data priority or treats isochronous data as asynchronous data, then those functions relying on real time data, such as motion-picture video, may not function satisfactorily. Alternatively, if a computer system prioritizes isochronous data, then the performance of the computer system can suffer since the latency of asynchronous data may become unacceptably long. As computer systems are called on to perform more and more real time activity, such as real time video, it becomes more critical that asynchronous and isochronous data be treated in a manner that prevents problems from occurring in the real time tasks without adversely effecting other aspects of computer performance.
In addition, as the number of functions integrated onto the integrated circuits of computer systems increases, the need for additional integrated circuit package pins also increases. Supporting the host bus, the memory interface, the PCI bus and a graphics interface results in a north bridge integrated circuit having a relatively large number of pins that is relatively unpopulated in terms of the number of transistors on the integrated circuit. The large number of pins requires the integrated circuit to be larger than would otherwise be necessary and therefore increases costs.
It would be desirable therefore, to have a deterministic high speed major interconnect bus providing improved quality of service for both isochronous and asynchronous traffic classes. It would also be desirable to reduce the pressure for additional pins on the integrated circuits making up the computer system.
SUMMARY OF THE INVENTION
Accordingly, a communication link is provided that carries transactions between functions over multiple logical pipes. Various logical pipe structures are possible. One embodiment of the invention provides a computer system that includes a first integrated circuit having at least a first function and a second integrated circuit having a plurality of second functions. The communication link connects the first integrated circuit and the second integrated circuit. The communication link includes at least one pipe having a source side on the first circuit and a target side on the second integrated circuit, the one pipe carrying transactions over the communication link between the first function and the second functions. The pipe is identified by a pipe identification carried in the transactions. A target side distributor circuit is coupled between the second functions and the communication link. The target side distributor circuit receives those transactions from the communication link having the pipe identification. The target side distributor circuit provides transactions received from the communication link having the pipe identification to respective ones of the second functions according to an address field included in the transactions.
In another embodiment of the invention a method is provided for communicating in a computer system. The method includes receiving a packet over an interconnect bus in a receive circuit. The packet includes a pipe identification identifying a logical pipe on which the packet is being carried. The received packet is routed to a target distributor circuit if the pipe identification corresponds to the logical pipe. The method further determines which of the functions is the appropriate destination for the command included in the packet according to an address that is contained in the packet and provides the command and any associated data to that function.
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Application No. 09/326,304, filed Jun. 4, 1999, listing Dale E. Gulick, Larry D. Hewitt, Alfred Hartmann, and Geoffrey S. S. Strongin as inventors, (claims only).
Application No. 09/330,527, filed Jun. 11, 1990, listing Dale E. Gulick and Geoffrey S. S. Strogin as inventors, (claims only).
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Compaq et al., “University Serial Bus Specification,”
Gulick Dale E.
Strongin Geoffrey S. S.
Advanced Micro Devices , Inc.
Lefkowitz Sumati
Zagorin O'Brien & Graham LLP
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