Target computer processor unit (CPU) determination during...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C711SE12057, C711SE12033

Reexamination Certificate

active

07958313

ABSTRACT:
A method, system, and computer program product for target computer processor unit (CPU) determination during cache injection using input/output (I/O) adapter resources are provided. The method includes storing locations of cache lines for pinned or affinity scheduled processes in a table on an input/output (I/O) adapter. The method also includes setting a cache injection hint in an input/output (I/O) transaction when an address in the I/O transaction is found in the table. The cache injection hint is set for performing direct cache injection. The method further includes entering a central processing unit (CPU) identifier and cache type in the I/O transaction, and updating a cache by injecting data values of the I/O transaction into the cache as determined by the CPU identifier and the cache type associated with the address in the table.

REFERENCES:
patent: 6243788 (2001-06-01), Franke et al.
patent: 6269390 (2001-07-01), Boland
patent: 6711651 (2004-03-01), Moreno et al.
patent: 7159077 (2007-01-01), Tu et al.
patent: 2004/0128450 (2004-07-01), Edirisooriya et al.
patent: 2005/0246500 (2005-11-01), Iyer et al.
patent: 2006/0064518 (2006-03-01), Bohrer et al.
patent: 2006/0085602 (2006-04-01), Huggahalli et al.
patent: 2006/0112238 (2006-05-01), Jamil et al.
patent: 2006/0136671 (2006-06-01), Balakrishnan et al.
patent: 2007/0156968 (2007-07-01), Madukkarumukumana et al.
patent: 2008/0065832 (2008-03-01), Srivastava et al.
patent: 2008/0104325 (2008-05-01), Narad et al.
patent: 2008/0127131 (2008-05-01), Gao et al.
patent: 2008/0229009 (2008-09-01), Gaither et al.
Khunjush et al., Lazy Direct-to-Cache Transfer during Receive Operations in a Message Passing Environment, ACM CF'06, May 3-5, 2006, pp. 331-340.
U.S. Appl. No. 11/958,418, filed Dec. 18, 2007.
U.S. Appl. No. 11/958,424, filed Dec. 18, 2007.
U.S. Appl. No. 11/958,435, filed Dec. 18, 2007.
U.S. Appl. No. 11/958,440, filed Dec. 18, 2007.
U.S. Appl. No. 11/958,445, filed Dec. 18, 2007.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Target computer processor unit (CPU) determination during... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Target computer processor unit (CPU) determination during..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Target computer processor unit (CPU) determination during... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2724537

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.