Taper isolated random access memory array and method of operatin

Details Taper isolated random access memory array and method of operatin Taper isolated random access memory array and method of operatin

1979-09-14

1981-09-22

Hecker, Stuart N.

Static information storage and retrieval

Systems using particular element

Semiconductive

365189, G11C 1140, G11C 700

Patent

active

042913918

ABSTRACT:
The present invention is embodied in a method of operating a dynamic random access memory (RAM) array having individual depletion mode metal-oxide-semiconductor (MOS) transistors as the memory cells. The cells can be programmed to two threshold states providing constant current sensing. Cell programming is by application of appropriate signals to the transistor gate electrode and source. Reading is accomplished by grounding the source and sensing current through the transistor. An intermediate voltage on the gate electrode prevents changes in the state of the cell.

REFERENCES:
patent: 3720925 (1973-03-01), Ross
patent: 3760378 (1973-09-01), Burns
patent: 4000504 (1976-12-01), Berger
patent: 4112507 (1978-09-01), White et al.

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