Static information storage and retrieval – Read/write circuit – Testing
Patent
1980-09-08
1983-04-19
Hecker, Stuart N.
Static information storage and retrieval
Read/write circuit
Testing
324158T, 371 21, G11C 2900
Patent
active
043808050
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention pertains to semiconductor integrated circuits and more particularly to a circuit for burn-in operation of such circuits for minimizing the number of external inputs required for burn-in operation.
BACKGROUND ART
Integrated semiconductor circuits have the potential for operating for long periods of time without failure. However, a substantial percentage of such circuits fail within the first few hours or days of operation due to marginal defects in manufacture. Such marginal circuits frequently test good under initial screening, but fail shortly thereafter. It is therefore incumbent upon the manufacturer of such circuits to burn-in each of the circuits for a period of time at elevated voltages and temperatures to cause failure of the marginal circuits before shipment. Without burn-in a substantial number of maginal circuits could be shipped to users and these circuits would be installed in the user's products only to fail a short time later. A failure of a component under such circumstances has severe economic impacts on both the user and the producer of integrated circuits.
Heretofore, integrated circuits have been burned-in after the circuits have been packaged in the manner that they will be delivered to the customer. A group of packaged circuits are mounted on a conventional circuit board which has a plurality of sockets. The board is then placed in an oven for operating the circuits under stress. Within the oven the integrated circuits are cycled through their operational states while an elevated voltage is supplied thereto and the temperature is set to a stress level. After operating for a fixed number of hours in this environment, most of the marginal circuits fail and these circuits are discarded. The remainder of the circuits have been proven reliable and can therefore safely be shipped to the customers.
As noted above, the burn-in of each individual circuit is essential but this is a very expensive process. For each marginal circuit that is discarded there is a complete loss of the labor involved in inserting the circuit into the package as well as the cost of the package itself. In mass production operations, a great number of test boards and ovens are required to accommodate the volume of circuits which are being manufactured. The ovens and stress testing boards together with the labor involved in the handling of the circuits represent a substantial manufacturing expense.
In view of these problems there exists a need for apparatus for burn-in of integrated semiconductor memory circuits to reduce the labor required for such burn-in and to prevent the loss of packages for defective circuits.
DISCLOSURE OF THE INVENTION
A circuit is disclosed for burning-in an integrated circuit which has a first set of terminals for receiving signals for normal operation of the integrated circuit. The burn-in circuit receives an externally produced burn-in command and generates a test signal. in response to the test signal the burn-in circuit receives signals through a second set of terminals, which may comprise a subset of the first set of terminals, to exercise the majority of the components of the integrated circuit. The second set comprises fewer terminals than the first set and the second set has, for example, four terminals. This circuit permits a plurality of integrated circuits to be burned-in concurrently while mounted on a tape having a single metallization layer.
BRIEF DESCRIPTION OF THE DRAWINGS
For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following detailed description taken in conjunction with the accompanying drawings in which:
FIG. 1 is a plan view of a burn-in tape having an integrated circuit semiconductor memory connected thereto; and
FIG. 2 is a schematic diagram of a burn in circuit for use in conjunction with the tape of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
A procedure termed "tape bonding" has been widely used in the semiconductor industry for conn
REFERENCES:
patent: 3961251 (1976-06-01), Hurley et al.
patent: 3961252 (1976-06-01), Eichelberger
patent: 3969706 (1976-07-01), Proebsting
patent: 4183096 (1980-01-01), Cenker et al.
patent: 4243937 (1981-01-01), Multani et al.
Kelley, "Imbedded Memory Test Methods", IBM Tech. Disc. Bul., vol. 21, No. 12, 5/79, pp. 4911-4913.
Aichelmann et al., "Memory Initialization by Deferred Refresh", IBM Tech. Disc. Bul., vol. 18, No. 5, 10/75, p. 1457.
Hecker Stuart N.
Mostek Corporation
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