Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-02-06
2002-08-13
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S532000, C257S753000, C257S762000, C257S773000
Reexamination Certificate
active
06433379
ABSTRACT:
TECHNICAL FIELD
The present invention relates to integrated circuit fabrication in general and in particular to a method for forming an in-laid copper metallization capacitor within an integrated circuit.
BACKGROUND OF THE INVENTION
There is an increasing demand for miniaturization in the integrated circuits industry. This demand has led to an ever constant reduction in the size of integrated circuit (IC) components. Such reduction in the size of the components provides for lower cost manufacture due to smaller chip size and increased yield, as well as improved circuit performance in many instances.
However, reduction in the size of some integrated circuit devices can lead to undesired results. For example, reduction in the size of a storage capacitor necessarily reduces the capacitance thereof and reduces the amount of charge which may be stored thereupon for a given bias voltage. In particular, in a conventional dynamic random access memory (DRAM) device, the charge stored by an individual memory cell must be maintained at as large a value as possible, in order for the DRAM to tolerate causes of “soft” errors, i.e., data loss, due to the impingement of alpha particles and other charged particles upon the memory device. In order to maintain the storage capacitance when the capacitor surface area is reduced, various techniques such as reduction of the dielectric thickness, and increase of the bias voltage have been used. However, the reliability of the storage capacitor is adversely affected by either of such techniques, as tunneling of the stored charge increases directly with the applied voltage and inversely with the thickness of the dielectric.
One technique for increasing the capacitance of a storage capacitor is to use dielectric materials with high dielectric constants. Tantalum pentoxide (Ta
2
O
5
) is an example of such a material, as its dielectric constant of 22 is five times higher than that of silicon dioxide, which is a conventional storage capacitor dielectric. However, Ta
2
O
5
is not always a compatible material for the manufacture of modern integrated circuits, as it tends to crystallize, resulting in increased leakage at a relatively low temperature for modern integrated circuit processing.
Since market forces are driving the integrated circuitry towards increasing operating speeds while decreasing capacitor size, it would be desirable to have a method of fabricating a capacitor structure which satisfies the increasing market demands for smaller device sizes and which provides improved filtering, timing and energy storage function.
SUMMARY OF THE INVENTION
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention relates to a method for forming an in-laid copper metallization capacitor preferably in a trench serpentine formation. The present invention accomplishes this end by using a tantalum anodization process which is compatible with a dual or single copper in-laid (damascene) approach.
In one aspect of the present invention, the method includes providing a semiconductor substrate having at least one trench formed therein. A first metal layer is deposited conformally onto the trench and substrate surface. The first metal layer is then anodized to form a conformal bilayer comprising an anodic (metal) oxide layer formed over the first metal layer. A copper-conductive metal layer is then deposited conformally over the metal oxide layer to facilitate electroplating of the trench and substrate surface. The at least one trench and substrate surface is then electroplated with copper whereby the trench is filled with copper.
In another aspect, the invention provides a method for forming an-laid copper metallization capacitor in a trench serpentine formation. The method comprises providing a semiconductor substrate having at least one trench etched therein. A tantalum layer is then deposited conformally to the trench and over the substrate. The tantalum layer then undergoes anodization, thereby forming a conformal bilayer in the at least one trench and over the substrate comprising a tantalum pentoxide layer formed over the tantalum layer.
A copper-tantalum layer is then deposited over the bilayer to form a conformal base surface suitable for electroplating. The surface, including the at least one trench and the substrate surface, is then electroplated with copper wherein the at least one trench is filled with copper. Following electroplating, the substrate surface undergoes chemical mechanical polishing (CMP) to remove the copper-tantalum, tantalum pentoxide layer and the tantalum layer from the substrate surface. A post-CMP cleaning may also be done to remove any residues associated the copper-tantalum, tantalum and tantalum pentoxide metals.
In yet another aspect, the present invention provides a system for an in-laid copper metallization capacitor containing a seed layer deposited conformally to at least one trench formed in a semiconductor substrate. A seed oxide layer is formed conformally on the seed layer. An adhesion layer is deposited conformally on the seed oxide layer, wherein the seed layer, the seed oxide layer and the adhesion layer facilitate mitigation of shorts and current leakage; and copper which is electroplated onto the substrate to fill the at least one trench.
In still another aspect, the present invention provides a system for an in-laid copper metallization capacitor containing a first tantalum layer deposited conformally to at least one trench formed in a semiconductor substrate. A tantalum pentoxide layer is then formed conformally on the first metal layer. A second tantalum layer is deposited conformally on the tantalum pentoxide layer, wherein the first tantalum layer, the tantalum pentoxide layer and the second tantalum layer facilitate mitigation and elimination of shorts and current leakage; and copper which has been electroplated onto the substrate fills the at least one trench.
The invention extends to features hereinafter fully described and features particularly pointed out in the claims. The following detailed description and the annexed drawings set forth in detail certain illustrative examples of the invention. These examples are indicative of but a few of the various ways in which the principles of the invention may be employed. Other ways in which the principles of the invention may be employed and other objects, advantages and novel features of the invention will be apparent from the detailed description of the invention when consider in conjunction with the drawings.
REFERENCES:
patent: 5595937 (1997-01-01), Mikagi
patent: 6033982 (2000-03-01), Lopatin et al.
patent: 6146517 (2000-11-01), Hoinkis
Avanzino Steven C.
Buynoski Matthew
Lopatin Sergey
Xiang Qi
Advanced Micro Devices , Inc.
Amin & Turocy LLP
Wojciechowicz Edward
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