Electrical computers and digital processing systems: support – Multiple computer communication using cryptography – Protection at a particular protocol layer
Reexamination Certificate
1997-09-05
2001-03-20
Wright, Norman M. (Department: 2785)
Electrical computers and digital processing systems: support
Multiple computer communication using cryptography
Protection at a particular protocol layer
C380S001000, C380S030000
Reexamination Certificate
active
06205550
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of system security. More specifically, the present invention relates to the tamper resistant methods and apparatus.
2. Background Information
Many applications, e.g. financial transactions, unattended authorizations and content management, require the basic integrity of their operations to be assumed, or at least verified. While a number of security approaches such as encryption and decryption techniques are known in the art, unfortunately, the security approaches can be readily compromised, because these applications and the security approaches are implemented on systems with an open and accessible architecture, that renders both hardware and software including the security approaches observable and modifiable by a malevolent user or a malicious program.
Thus, a system based on open and accessible architecture is a fundamentally insecure platform, notwithstanding the employment of security measures. However, openness and accessibility offer a number of advantages, contributing to these systems' successes. Therefore, what is required are techniques that will render software execution virtually unobservable or unmodifiable on these fundamentally insecure platforms, notwithstanding their openness and accessibility.
SUMMARY OF THE INVENTION
In one apparatus, a number of obfuscated programming instructions are equipped to self-verify whether execution of the obfuscated programming instructions is being observed.
In another apparatus, a number of obfuscated programming instruction are equipped to determine whether the apparatus is being operated in a mode that supports single step execution of the obfuscated programming instructions.
In yet another apparatus, a number of obfuscated programming instruction are equipped to verify whether an amount of elapsed execution time has exceeded a threshold.
In yet another apparatus, a first and a second group of obfuscated programming instruction are provided to implement a first and a second tamper resistant technique respectively, with the first and the second group of programming instructions sharing a storage location for a first and a second key value corresponding to the first and the second tamper resistant technique.
REFERENCES:
patent: 4634807 (1987-01-01), Chorley et al.
patent: 4786790 (1988-11-01), Kruse et al.
patent: 4847902 (1989-07-01), Hampson
patent: 4866665 (1989-09-01), Haswell-Smith
patent: 4926480 (1990-05-01), Chaum
patent: 4947430 (1990-08-01), Chaum
patent: 5081675 (1992-01-01), Kittirutsunetorn
patent: 5136643 (1992-08-01), Fischer
patent: 5224160 (1993-06-01), Paulini et al.
patent: 5265164 (1993-11-01), Matyas et al.
patent: 5267312 (1993-11-01), Thompson
patent: 5343527 (1994-08-01), Moore
patent: 5347579 (1994-09-01), Blandford
patent: 5421006 (1995-05-01), Jablon
patent: 5469507 (1995-11-01), Canetti et al.
patent: 5483649 (1996-01-01), Kuznetsov et al.
patent: 5535276 (1996-07-01), Ganesan
patent: 5559960 (1996-09-01), Lettvin
patent: 5638446 (1997-06-01), Rubin
patent: 5652793 (1997-07-01), Priem
patent: 5668874 (1997-09-01), Kristol et al.
patent: 5684875 (1997-11-01), Ellenberger
patent: 5768382 (1998-06-01), Schneier
patent: 5822431 (1998-11-01), Sprunk
patent: 5966306 (1999-10-01), Nodine et al.
patent: 6006328 (1999-12-01), Drake
patent: 6049609 (2000-04-01), Maliszewski
Radai, Yisael, “Integrity Checking for Anti-Viral Purposes Theory and Practice,” Dec. 26, 1994, see Sections 1, 2, 3, and 8.
Aucsmith David W.
Graunke Gary L.
Maliszewski Richard L.
Mangold Richard P.
Nardone Joseph M.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Wright Norman M.
LandOfFree
Tamper resistant methods and apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Tamper resistant methods and apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Tamper resistant methods and apparatus will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2473057