Tamper-resistant method and data processing system using the...

Details Tamper-resistant method and data processing system using the... Tamper-resistant method and data processing system using the...

2005-11-15

2005-11-15

Moazzami, Nasser (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S163000, C711S167000, C713S194000, C713S322000, C365S233100

Reexamination Certificate

active

06965977

ABSTRACT:
A tamper-resistant method for preventing tampering using a glitch attack and a data processing system using the same are provided. The method includes reading out a first data from a region of the memory assigned by an address; reading out a second data from the region of the memory assigned by the address; determining whether the first data is identical to the second data; and fetching by the processor either one of the first and second data when the first data is identical to the second data.

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patent: 5475855 (1995-12-01), Uesugi
patent: 5808961 (1998-09-01), Sawada
patent: 6606707 (2003-08-01), Hirota et al.
patent: 61040652 (1986-02-01), None
patent: 63165936 (1988-07-01), None

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