Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2000-04-19
2003-04-22
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S114000, C711S118000, C711S202000
Reexamination Certificate
active
06553457
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to disk drive performance features and more particularly to a disk drive having a cache control system for improving the disk drive's response time to host commands.
2. Description of the Prior Art
A host computer stores and accesses data on a disk drive by issuing commands to the disk drive over a standardized interface. The smallest indivisible data unit addressable on a disk is a logical block or disk sector, typically of 512 bytes, and each such disk sector is assigned a logical block address (LBA). When the host computer sends a command to the disk drive, the nature of the command is specified, e.g., read or write, along with a start LBA and a count specifying the number of contiguous sectors to be transferred.
Existing disk drives typically have a semiconductor cache memory for temporarily storing disk data that is likely to be requested by a host computer. The response time latency for storing and accessing data in a semiconductor memory is much smaller than the response time latency for mechanically storing and accessing data stored on a rotating disk. In existing disk drives, if the entire LBA range specified by a host command cannot be stored in a contiguous segment in the cache memory, then a sufficiently large contiguous segment in the cache memory must be allocated and configured for responding to the host command. The disk drive's response to the host command may be delayed while the contiguous segment is formed.
Accordingly, there exists a need for a disk drive having a disk cache architecture for efficiently configuring memory segments for effectively responding to host commands. The present invention satisfies these needs.
SUMMARY OF THE INVENTION
The present invention is embodied in a disk drive having a cache control system that is configured to effectively and efficiently respond to host commands by forming variable length segments of memory clusters for caching disk data in contiguous ranges of logical block addresses without regard to the sequential order of the memory clusters. The cache control system has a tag memory usable only for defining the segments.
An embodiment of the invention may reside in a disk drive having a cache memory and the cache control system. The cache memory has a plurality of sequentially-ordered memory clusters for caching disk data of disk sectors identified by logical block addresses. The cache control system has a tag memory only usable and configured to define variable length segments of memory clusters. Each segment is for caching disk data of a contiguous range of logical block addresses using the memory clusters without regard to the sequential order of the memory clusters.
The disk drive may further include a plurality of cluster control blocks with each cluster control block being associated with a particular cluster of the cache memory. The tag memory may define each segment using the cluster control blocks. Each cluster control block that is associated with a segment is configured to point to a subsequent cluster control block or to indicate an end cluster control block of the segment. The tag memory may include a tag record associated with each segment for pointing to a first cluster control block associated with a first logical block address, and to a last cluster control block associated with a last logical block address of the associated segment or to an allocated count associated with a length of the associated segment. The tag record may also indicate a cache state of the disk data in a segment.
The disk drive also may include a scan engine, a microprocessor, or a host writable control store for accessing the tag records in the tag memory, and may further include means for arbitrating access to the tag records between the scan engine, the microprocessor, and the host writable control store.
REFERENCES:
patent: 5713003 (1998-01-01), DeWitt et al.
patent: 5717888 (1998-02-01), Candelaria et al.
patent: 5765204 (1998-06-01), Bakke et al.
patent: 5875352 (1999-02-01), Gentry et al.
patent: 5875454 (1999-02-01), Craft et al.
patent: 6018789 (2000-01-01), Sokolov et al.
patent: 6092150 (2000-07-01), Sokolov et al.
Castro Ralph H.
Ng Tsun Y.
Wilkins Virgil V.
Fawcett, Esq. Robroy R.
Peugh Brian R.
Shara, Esq. Milad G.
Western Digital Technologies Inc.
Yoo Do Hyun
LandOfFree
Tag memory disk cache architecture does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Tag memory disk cache architecture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Tag memory disk cache architecture will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3013186