Table-based scheduler for FIFOs and the like

Details Table-based scheduler for FIFOs and the like Table-based scheduler for FIFOs and the like

2007-06-19

2007-06-19

Choi, Woo H. (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S220000, C711S221000

Reexamination Certificate

active

10809180

ABSTRACT:
A scheduler for a set of data packet storage devices (e.g., FIFOs) implements a scheduling algorithm embodied in a look-up table (LUT) that identifies the next FIFO to select for service based on the current status of the FIFOs. In one embodiment, in addition to a memory device used to store the LUT, the scheduler has (1) a latch adapted to store and forward the LUT output and (2) an extractor that implements a finite state machine that determines (1) when to enable the latch and (2) when to forward the identification of the next FIFO to select for service to the set of FIFOs. Using a LUT enables relatively complicated scheduling algorithms to be implemented for relatively large numbers of FIFOs without significantly increasing the execution time of the scheduler.

REFERENCES:
patent: 5982776 (1999-11-01), Manning et al.
patent: 6732206 (2004-05-01), Jensen et al.
patent: 2005/0122982 (2005-06-01), Li et al.

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