Tab tape and method of manufacturing the same

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds

Reexamination Certificate

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Details

C257S040000, C257S203000, C438S015000

Reexamination Certificate

active

07414323

ABSTRACT:
Input test pads of an adjacent pattern area are placed in a vacant area of a layout area of output test pads, optimizing the layout area of test pads for use in inspection of a semiconductor chip. Thus, it is possible to miniaturize a semiconductor package.

REFERENCES:
patent: 7132841 (2006-11-01), Bertin et al.
patent: 2006/0208350 (2006-09-01), Poo et al.
patent: 8-24586 (1996-01-01), None

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