Tab semiconductor package with cushioned land grid array outer l

Details Tab semiconductor package with cushioned land grid array outer l Tab semiconductor package with cushioned land grid array outer l

1993-07-30

1995-02-28

James, Andrew J.

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

257668, 257692, 257734, 257737, 257738, 257778, 257780, H01L 2348, H01L 2944, H01L 2952, H01L 2960

Patent

active

053940091

ABSTRACT:
A film of elastomeric material is used to laminate the tape with LGA outer lead bumps to the stiffner plate of the semiconductor package. The elastomeric material has the necessary physical and electrical characteristics to provide the required firmness to maintain good electrical contact between the outer lead bumps and the corresponding contacting pads on a socket, ceramic substrate or PWB, and at the same time, to provide the required resilience to accommodate differences in heights between the outer lead bumps. The stiffner plate is fabricated with a cavity at its center for accommodating the VLSI die, and slots along the outer edges of its underside for storing the excess elastomeric material squeezed out when laminating the tape to the stiffner plate, thereby preventing the excess squeezed out elastomeric material from building up at the outer edges of the semiconductor package to a height in excess of the outer lead bumps. As a result, the land pattern on the socket, ceramic substrate or PWB is not required to address the differences in heights between the outer lead bumps.

REFERENCES:
patent: 5243223 (1993-09-01), Yamada et al.
Lau, John H., et al. Overview of Tape Automated Bonding Technology, Electronic Material Handbook, vol. 1 Packaging, pp. 274-285.

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