Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2001-02-16
2003-01-21
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S574000, C438S579000, C438S588000, C438S592000
Reexamination Certificate
active
06509253
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to an integrated circuit (IC) and the fabrication of an integrated circuit. More particularly, the present invention relates to an integrated circuit having transistors with gate conductors having reduced resistance.
BACKGROUND OF THE INVENTION
Transistors are generally complementary metal oxide semiconductor field effect transistors (MOSFETs). An exemplary drawing of a conventional transistor is shown in
FIGS. 1 and 2
. A transistor
100
includes a gate conductor
102
disposed between a source region
108
and a drain region
110
. Source region
108
and drain region
110
are formed in a semiconductor substrate
114
.
Gate conductor
102
is provided over a thin gate oxide material
104
. Gate conductor
102
can be a metal, polysilicon, polysilicon/germanium (Si
x
Ge
(1-x)
) material that controls charge carriers in a channel region
116
between the drain and the source to turn the transistor on and off. The transistors can be N-channel MOSFETs or P-channel MOSFETs.
Generally, it is desirous to manufacture smaller transistors to increase the component density on an integrated circuit. For example, gate conductors, conductive lines, vias, doped regions, and other structures associated with an integrated circuit can all be reduced in size to increase component density. As transistors are reduced in size (CMOS scaling), resistance associated with conductive elements has increases.
When certain conductive structures, such as, gate conductors, are reduced in size, the cross-sectional dimensions are also reduced. For example, as gate widths become smaller, the cross-sectional width of the gate conductor becomes smaller. Further, as the thickness of layers becomes smaller, the height of gate conductors is decreased. Therefore, reduction in size of the gate conductor reduces the cross-sectional area of the conductor.
A reduction in cross-sectional dimensions increases the resistive characteristics of the gate conductor (e.g., sheet resistance). As the size of features on the integrated circuit reach sizes below 50 nanometers, gate conductor resistance becomes a larger problem at gate lengths of less than 50 nm. Higher resistance results in a greater voltage drop across gate conductor
102
. The greater voltage drop degrades speed and increases the amount of power consumed by transistor
100
.
Gate resistance can be manifested in at least two fashions across gate conductor
102
. First, increased series resistance from a top surface
122
to a bottom surface
124
is disadvantageous because of the increased voltage drop. Further, the resistance between a gate contact and surface
102
can add to this resistance. Second, increased resistance from end
130
to another end
132
of gate conductor
104
can increase the voltage drop between ends
130
and
132
. This resistance also can increase the voltage drop associated with gate conductor
102
, thereby degrading speed and increasing the amount of power consumed by transistor
100
.
Heretofore, a silicide layer has been provided on surface
122
to reduce series resistance associated with gate conductor
102
. The silicide layer is simultaneously provided on source region
108
, drain region
110
and gate conductor
102
. A low thermal budget is utilized in post-source region
108
and drain region
110
processes to reduce dopant diffusion and preserve shallow junction formation. Accordingly, the silicide layers for drain region
108
and source region
110
and consequently gate conductor
102
are formed in a less silicon consuming fashion. Accordingly, conventional processes cannot utilize a thicker silicide region to achieve smaller series resistance in the gate conductor.
Further, resistance problems can be exacerbated by dopant activation and diffusion phenomena associated with the gate conductor. Low dopant activation diffusion can be related to the low thermal budget required to maintain shallow junction formation. Low levels of active dopant in the gate conductor increase the resistance of the gate conductor.
The dopant concentration near the gate electrode/gate oxide interface is often relatively low. The relatively low dopant concentration near the gate electrode/the gate oxide interface is referred to as “gate depletion-effect” and is a major problem in complimentary MOS (CMOS) processes which manufacture small-scale transistors. Polysilicon/ germanium gate conductors have been employed to reduce gate depletion effect.
Thus, there is a need for a transistor which has reduced gate resistance. Further still, there is a need for a transistor with reduced gate sheet resistance. Further still, there is a need for a process that more effectively suicides the gate conductor. Even further still, there is a need for a method of making a novel transistor structure which is less susceptible to gate resistance and yet has an acceptable size. Even further still, there is a need for a germanium, polysilicon, or polysilicon/germanium gate conductor that can be efficiently manufactured and yet has reduced resistance.
SUMMARY OF THE INVENTION
An exemplary embodiment relates to a method of manufacturing an integrated circuit. The method includes providing an insulative layer above a gate structure and a top surface of a substrate, removing the insulative layer to expose the gate structure, providing a gate conductor layer above a top surface of the insulative layer, and etching the gate conductor layer to form a T-shaped gate conductor. The top surface of the substrate includes a silicided drain region. The gate structure has a top surface above a top surface of the insulative layer after the insulative layer is removed.
Another exemplary embodiment relates to a method of manufacturing an ultra-large scale and engraved circuit. The integrated circuit includes a transistor with a T-shaped gate conductor. The method includes steps of: providing an insulative layer above a gate structure on a top surface of a substrate, reducing a thickness of the insulative layer, and providing a second gate conductor. The gate structure includes a first gate conductor having a rectangular-shaped cross section of a first width. The thickness of the insulative layer is reduced until a top surface of the first gate conductor is above a top surface of the insulative layer. The second gate conductor is provided above the first gate conductor to form the T-shaped gate conductor. The T-shaped gate conductor has a second width at a top surface more than the first width.
Another exemplary embodiment relates to a transistor. The transistor includes a silicided source region, a silicided drain region, and a gate structure. The gate structure has a T-shaped conductor. The T-shaped conductor has a silicided top portion. The silicided top portion has different silicidation characteristics than the silicided source region and the silicided drain region.
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“Ultra-Thin-Body Silicon-On-Insulator MOSFET's for Terabit-Scale Integration” by Yu, et al, Department of Electrical Engineering & Computer Sciences.
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Elms Richard
Foley & Lardner
Luhrs Michael K.
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