Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-01-16
2003-04-22
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S140000, C257S141000, C257S162000
Reexamination Certificate
active
06552398
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of integrated circuit (IC) design. Specifically, it relates to a Thyristor Random Access Memory (T-RAM) array having a planar cell structure and method for fabricating the same.
BACKGROUND OF THE INVENTION
A low-power, high-speed and high-density negative differential resistance (NDR) based (NDR-based) SRAM cell which can provide DRAM-like densities at SRAM-like speeds has been proposed by Farid Nemati and James D. Plummer in “A Novel High Density, Low Voltage SRAM Cell with a Vertical NDR Device,” 1998 Symposium on VLSI Technology Digest of Technical Papers, EEE, pages 66-67, 1998.
The memory device structure is shown by FIG.
1
and is designated by reference numeral
10
; the memory device structure is called a Thyristor-based Random Access Memory (T-RAM) cell. The T-RAM cell
10
consists of a thin vertical pnpn thyristor
12
with a surrounding nMOS gate
14
as the bistable element and a planar nMOSFET as the access transistor
16
. The circuit schematic of the T-RAM cell
10
is shown by FIG.
2
.
To access the T-RAM cell
10
, two wordlines are necessary. The first wordline WL
1
is used to control an access gate of the transfer nMOSFET device
16
, while the second wordline WL
2
is the surrounding nMOS gate
14
which is used to control the switch of the vertical pnpn thyristor
12
. The thyristor
12
is connected to a reference voltage Vref. The second wordline WL
2
improves the switching speed of the thyristor
12
from 40 ns to 4 ns with a switching voltage. A bitline BL connects the T-RAM cell
10
to a sense amplifier for reading and writing data from and to the T-RAM cell
10
. The T-RAM cell
10
exhibits a very low standby current in the range of 10 pA.
When writing a “high”, the bitline BL is set at low, and both wordlines WL
1
, WL
2
are switched on. At this moment, the thyristor
12
behaves like a forward biased pn diode. After a write operation, both gates are shut off, and a “high” state is stored in the thyristor
12
. In a read operation, only the first wordline WL
1
is activated, a large “on” current will read on the bitline BL through the access gate. When writing a “low”, the bitline BL is set at “high” state, and both wordlines WL
1
, WL
2
are switched on. At this moment, the thyristor
12
behaves like a reverse biased diode. After the write operation, both gates are shut off, and a “low” state is stored in the thyristor
12
. Similarly, in a consequence read, a very low current will be detected on the bitline BL. Further details of the operation of the T-RAM cell
10
and its gate-assisted switching are described in Nemati et al.; the contents of which are incorporated herein by reference.
A T-RAM array having a plurality of T-RAM cells
10
has demonstrated a density equivalent to that of DRAM arrays and a speed equivalent to that of SRAM arrays. Hence, the T-RAM array provides advantages afforded by both SRAM and DRAM arrays. These advantages make T-RAM an attractive choice for future generations of high speed, low-voltage, and high-density memories and ASICs.
However, there are several drawbacks of the T-RAM cell
10
. First, there is the requirement of forming the thyristor
12
having a vertical pillar on a substrate during a fabrication process. Difficulties arise in controlling the dimensions of the vertical pillar and reproducing these dimensions for each T-RAM cell
10
in the T-RAM array. Second, due to the existence of a vertical thyristor
12
in each T-RAM cell
10
, each T-RAM cell
10
is not planar and therefore difficult to scale. Third, it is difficult to control the dimension while forming the surrounding gate around the base of each vertical thyristor
12
. Finally, due to these drawbacks, the resulting T-RAM cell
10
cannot be smaller than 8F
2
.
SUMMARY
An aspect of the present invention is to provide a T-RAM array having a planar cell structure for overcoming the disadvantages of the prior art.
Another aspect of the present invention is to provide a T-RAM array having a plurality of T-RAM cells, wherein each of the plurality of T-RAM cells has a planar cell structure.
Also, another aspect of the present invention is to provide a memory system having a plurality of T-RAM cells arranged in an array, wherein each of the plurality of T-RAM cells has a planar cell structure.
Finally, another aspect of the present invention is to provide a method for fabricating a T-RAM array having a planar cell structure.
Accordingly, in an embodiment of the present invention, a T-RAM array having a planar cell structure is presented.
In another embodiment of the present invention, a T-RAM array having a plurality of T-RAM cells is presented, wherein each of the T-RAM cells has a planar cell structure.
Further, in another embodiment of the present invention, a memory system having a plurality of T-RAM cells arranged in an array, wherein each of the T-RAM cells has a planar cell structure.
Further still, in another embodiment of the present invention, a method is presented for fabricating a T-RAM array having a planar cell structure. Each of the T-RAM cells in the T-RAM array is fabricated by using doped polysilicon to form a self-aligned diffusion region to create a low-contact resistance p+ diffusion region. A silicided p+ polysilicon wire is preferably used to connect each of the plurality of the T-RAM cells to a reference voltage Vref A self-aligned junction region is formed between every two wordlines by implanting a n+ implant into a gap between every two wordlines. The self-aligned junction region provides for a reduction in the T-RAM cell size from a cell size of 8F
2
for a prior art T-RAM cell to a cell size of less than or equal to 6F
2
. Preferably, the T-RAM array is built on a semiconductor silicon-on-insulator (SOI) wafer to reduce junction capacitance and improve scalability.
REFERENCES:
patent: 5824584 (1998-10-01), Chen et al.
patent: 6104045 (2000-08-01), Forbes et al.
A Novel-Thyristor-based SRAM cell(T-RAM)for High-Speed, Low-Voltage, Giga-scale Memoriesby Farid Nemati and James D. Plummer, Center for Integrated Systems, Stanford, University, 1999.
A Novel High Density, Low Voltage SRAM Cell with a Vertical NDR Device, by Farid Nemati and James D. Plummer, Center for Integrated Systems, Stanford University, 1998.
Assaderaghi Fariborz
Hsu Louis L.
Joshi Rajiv V.
Dilworth & Barrese LLP
IBM Corporation
LandOfFree
T-Ram array having a planar cell structure and method for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with T-Ram array having a planar cell structure and method for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and T-Ram array having a planar cell structure and method for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3064284