Systolic array

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364200, 364754, G06F 738

Patent

active

047275030

ABSTRACT:
A systolic array of cells for processing a data stream includes an arrangement of nearest-neighbor connected boundary cells, internal cells and a multiplier, arranged as a triangular array and a column. The boundary cells are diagonally interconnected. Each boundary cell evaluates sine and cosine rotation parameters from data received from above for lateral transfer to a neighboring internal cell, and multiplies a diagonal input by the cosine parameter for diagonal output. Each internal cell receives rotation parameters from the left, applies them to data from above to produce an output below, and passes them on laterally. Data input to the column becomes cumulatively rotated before output from the final downstream internal cell. The final downstream boundary cell provides cumulatively multiplied cosine parameters. The multiplier provides the product of the outputs of these final cells. The product is the least squares residual arising from weighted minimization of input signals.

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patent: 4493048 (1985-01-01), Kung et al.
patent: 4533993 (1985-08-01), McCanny et al.
patent: 4544229 (1985-10-01), Verber
patent: 4544230 (1985-10-01), Caulfield
patent: 4588255 (1986-05-01), Tur et al.
Algorithms for VLSI Processor Arrays, H. T. Kung and Charles Leiserson, pp. 271-293.
Least Squares Computations by Given Transformations Without Square Roots, W. Morven Gentleman (1973), pp. 329-336.
Matrix Triangularization by Systolic Arrays, W. M. Gentleman, H. T. Kung (1981), pp. 19-26.

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