Memory system with redundancy for error avoidance

Details Memory system with redundancy for error avoidance Memory system with redundancy for error avoidance

1982-03-26

1984-08-07

Atkinson, Charles E.

Excavating

371 10, G06F 1110

Patent

active

044647549

ABSTRACT:
A memory system in which two or more memory modules containing the same information have their respective data outputs connected to the same data line. Each module includes means for checking the parity of the data being read-out at its output and in the event of a parity error indication effectively disconnects its output from the data line.

REFERENCES:
patent: 3245040 (1966-04-01), Burdett et al.
patent: 4051355 (1977-09-01), Lin

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