Electrical computers and digital data processing systems: input/ – Intrasystem connection – Protocol
Reexamination Certificate
2007-04-17
2007-04-17
Auve, Glenn A. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Protocol
C710S305000, C710S308000, C711S141000
Reexamination Certificate
active
10269922
ABSTRACT:
An apparatus may include a first system and a second system. The first system includes a first plurality of interface circuits, and each of the first plurality of interface circuits is configured to couple to a separate interface. The second system includes a second plurality of interface circuits, and each of the second plurality of interface circuits is configured to couple to a separate interface. A first interface circuit of the first plurality of interface circuits and a second interface circuit of the second plurality of interface circuits are coupled to a first interface. Both the first interface circuit and the second interface circuit are configured to communicate packets, coherency commands, and noncoherent commands on the first interface.
REFERENCES:
patent: 4630193 (1986-12-01), Kris
patent: 4788679 (1988-11-01), Kataoka et al.
patent: 5644753 (1997-07-01), Ebrahim et al.
patent: 5710907 (1998-01-01), Hagersten et al.
patent: 5797026 (1998-08-01), Rhodehamel et al.
patent: 5805590 (1998-09-01), Gillard et al.
patent: 5878268 (1999-03-01), Hagersten
patent: 5887138 (1999-03-01), Hagersten et al.
patent: 5920226 (1999-07-01), Mimura
patent: 5925097 (1999-07-01), Gopinath et al.
patent: 5961623 (1999-10-01), James et al.
patent: 5963745 (1999-10-01), Collins et al.
patent: 6009426 (1999-12-01), Jouenne et al.
patent: 6070215 (2000-05-01), Deschepper et al.
patent: 6094715 (2000-07-01), Wilkinson et al.
patent: 6101420 (2000-08-01), Van Doren et al.
patent: 6105119 (2000-08-01), Kerr et al.
patent: 6108739 (2000-08-01), James et al.
patent: 6108752 (2000-08-01), Van Doren et al.
patent: 6128728 (2000-10-01), Dowling
patent: 6138217 (2000-10-01), Hamaguchi
patent: 6182201 (2001-01-01), Arimilli et al.
patent: 6185520 (2001-02-01), Brown et al.
patent: 6195739 (2001-02-01), Wright et al.
patent: 6202132 (2001-03-01), Islam et al.
patent: 6209065 (2001-03-01), Van Doren et al.
patent: 6219755 (2001-04-01), Klein
patent: 6249846 (2001-06-01), Van Doren et al.
patent: 6266731 (2001-07-01), Riley et al.
patent: 6295057 (2001-09-01), Rosin et al.
patent: 6298370 (2001-10-01), Tang et al.
patent: 6338122 (2002-01-01), Baumgartner et al.
patent: 6449701 (2002-09-01), Cho
patent: 6681283 (2004-01-01), Thekkath et al.
patent: 2001/0039604 (2001-11-01), Takahashi
patent: 2002/0038407 (2002-03-01), Mounes-Toussi et al.
patent: 2003/0037224 (2003-02-01), Oehler et al.
patent: 2003/0097467 (2003-05-01), Sano
patent: 2003/0097498 (2003-05-01), Sano et al.
patent: 893 766 (1999-01-01), None
patent: 936 555 (1999-08-01), None
patent: 945 805 (1999-09-01), None
patent: 777 179 (2002-05-01), None
patent: 02025691.3 (2003-04-01), None
patent: 98/15155 (1998-04-01), None
patent: WO 00/38069 (2000-06-01), None
“HyperTransport Technology I/O Link”. White Paper, Advanced Micro Devices, Inc. Jul. 20, 2001. #25012A.
Wong, William. “High-Performance Processor Interconnect Gains Wide Support”. Electronic Design. Penton Media, Inc. Oct. 14, 2002. Retrieved from Internet Oct. 24, 2005. ED Online ID #1974. <http://www.elecdesign.com/Articles/Print.cfm?ArticleID=1974>.
Wong, William. “Quad 64-Bit Multiprocessor Targets Comm Applications”. Electronic Design. Penton Media, Inc. Oct. 14, 2002. Retrieved from Internet Oct. 24, 2005. ED Online ID #1968. <http://www.elecdesign.com/Articles/Print.cfm?ArticleID=1968>.
Levy, Markus. “Chip Combines Four 1 GHz Cores”. Microprocessor Report. Reed Electronics Group. Oct. 16, 2002.
European Search Report for EP26008 (02025686.3-2415-), mailed Feb. 27, 2003, 3 pages.
“They Design and Analysis of Dash: A Scalable Directory-Based Multiprocessor”, Daniel Lenoski, Dec. 1991, A Dissertation submitted to the Dept. of Elect. Engin. And the committee on graduate studies of Stanford Univ., 176 pages.
“An Argument for Simple COMA,” Saulsbury, et al., Aug. 1, 1994, SISC Research Report No. R94:15, 20 pages.
Tom R. Halfhill, “SiByte Reveals 64-Bit Core For NPUs; Independent MIPS64 Design Combines Low Power, High Performance,” Microdesign Resources, Jun. 2000, Microprocessor Report, 4 pages.
SiByte, “Target Applications,” http://sibyte.com/mercurian/applications.htm, Jan. 15, 2001, 2 pages.
SiByte, “SiByte Technology,” http://sibyte.com/mercurian/technology.htm, Jan. 15, 2001, 3 pages.
SiByte, “The Mercurian Processor,” http://sibyte.com/mercurian, Jan. 15, 2001, 2 pages.
SiByte, “Fact Sheet,” SB-1 CPU, Oct. 2000, rev. 0.1, 1 page.
SiByte, “Fact Sheet,” SB-1250, Oct. 2000, rev. 0.2, 10 pages.
Stepanian, SiByte, SiByte SB-1 MIPS64 CPU Core, Embedded Processor Forum 2000, Jun. 13, 2000, 15 pages.
Jack Keller, “The Mercurian Processor: A High Performance, Power-Efficient CMP for Networking,” Oct. 10, 2000, 22 pages.
Intel, “21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller,” Hardware Reference Manual, Revision 1.0, Oct. 1998, 219 pages.
Giorgi et al.; PSCR: A Coherence Protocol for Eliminating Passive Sharing in Shared-Bus Shared-Memory Multiprocessors; IEEE Transactions on Parallel and Distributed Systems; vol. 10, No. 7, Jul. 1999.
Gulati Manu
Moll Laurent R.
Rowlands Joseph B.
Sano Barton J.
Auve Glenn A.
Broadcom Corporation
Cleary Thomas J.
Garlick & Harrison & Markison
LandOfFree
Systems using mix of packet, coherent, and noncoherent... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Systems using mix of packet, coherent, and noncoherent..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Systems using mix of packet, coherent, and noncoherent... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3726738