Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-12-25
2007-12-25
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
11136256
ABSTRACT:
Systems, methods, and media for block-based assertion generation, qualification and analysis are disclosed. Embodiments may include a method for generating assertions for verifying a design. The embodiment may include generating session preferences, the session preferences including a selection of one or more assertion schemas for use in generating the assertions, where the selected assertion schema each have one or more design attributes. The embodiment may also include parsing the design to determine locations in the design for the assertions based on the design architecture, structure, and hierarchy and generating the assertions based on at least the session preferences, the determined locations for the assertions, and the design attributes associated with the selected assertion schema. Generating the assertions may further include analyzing and modifying existing assertions based on the session preferences and design attributes or qualifying the assertions for consistency and compliance with the session preferences and design attributes.
REFERENCES:
patent: 5907698 (1999-05-01), Kucukcakar et al.
patent: 6081864 (2000-06-01), Lowe et al.
patent: 6185723 (2001-02-01), Burks et al.
patent: 6247165 (2001-06-01), Wohl et al.
patent: 6321186 (2001-11-01), Yuan et al.
patent: 6449752 (2002-09-01), Baumgartner et al.
patent: 6553514 (2003-04-01), Baumgartner et al.
patent: 6560699 (2003-05-01), Konkle
patent: 6591402 (2003-07-01), Chandra et al.
patent: 6591403 (2003-07-01), Bass et al.
patent: 6609229 (2003-08-01), Ly et al.
patent: 6684359 (2004-01-01), Noy
patent: 6751583 (2004-06-01), Clarke et al.
patent: 2004/0181543 (2004-09-01), Wu et al.
patent: WO 03/100704 (2003-12-01), None
Accelerating “Concept to RTL for System-on-Chip Designs,” 2003 Synopsys, Inc., pp. 1-126.
Research Disclosure, “Large Pages Using Power PC BATs,” and “A Graphical Interface for Formulating CTL Rules for Model Checking,” International Business Machines Corporation, Jun. 1998. pp. 841-842.
Research Disclosure, “An Iterative Method to Reduce State Space for Efficient Formal Verification,” International Business Machines Corporation, Mar. 1998, p. 291.
Research Disclosure, “A Method to Optimize Environment Models in Format Verification,” International Business Machines Corporation, Apr. 1999, pp. 537-538.
Hekmatpour Amir
Salehi Azadeh
Cockburn Joscelyn G.
Do Thuan
International Business Machines - Corporation
Schubert Osterrieder & Nickelson PLLC
LandOfFree
Systems, methods, and media for block-based assertion... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Systems, methods, and media for block-based assertion..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Systems, methods, and media for block-based assertion... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3846259