Systems, methods, and media for block-based assertion...

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Optimization

Reexamination Certificate

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C716S104000, C716S106000, C716S119000

Reexamination Certificate

active

07900181

ABSTRACT:
Systems, methods, and media for block-based assertion generation, qualification and analysis are disclosed. Embodiments may include a method for generating assertions for verifying a design. The embodiment may include generating session preferences, the session preferences including a selection of one or more assertion schemas for use in generating the assertions, where the selected assertion schema each have one or more design attributes. The embodiment may also include parsing the design to determine locations in the design for the assertions based on the design architecture, structure, and hierarchy and generating the assertions based on at least the session preferences, the determined locations for the assertions, and the design attributes associated with the selected assertion schema. Generating the assertions may further include analyzing and modifying existing assertions based on the session preferences and design attributes or qualifying the assertions for consistency and compliance with the session preferences and design attributes.

REFERENCES:
patent: 6591402 (2003-07-01), Chandra et al.

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