Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package
Reexamination Certificate
2002-06-28
2004-09-14
Clark, Jasmine (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
C257S723000, C257S783000, C439S066000
Reexamination Certificate
active
06791171
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the field of integrated circuit (IC) package and wafer design, as well as to the fields of interconnection, testing and burn-in structures and processes. More particularly, the invention relates to improvements in photolithography-patterned spring contacts and enhanced system interconnect assemblies having photolithography-patterned spring contacts for use in the testing or burn-in of integrated circuits, and for interconnecting a large number of signals between electronic systems or subsystems.
BACKGROUND OF THE INVENTION
Integrated circuits are typically tested in wafer form (wafer sort) before they are packaged. During wafer sort, integrated circuits are tested one or few at a time, even though there may be hundreds or even thousands of the same integrated circuit located on a wafer. The packaged integrated circuits are then tested again, and burned-in, if necessary.
Prior to dicing the integrated circuits into individual dice on the wafer, the integrated circuits are placed (built) precisely on the wafer, but after dicing and separating the integrated circuits into individual dice for packaging and test, the packaged dices are handled individually, loosing the parallelism in handling.
Parallel testing on the wafer level has been limited in number and has so far been limited to low pin count devices, due to the difficulty in managing the large number of interconnects, and the limited amount of electronics which can conventionally be placed close to a wafer under test.
Attempts have also been made to burn-in ICs while in the wafer form. However, wafer-level burn-in is plagued with multiple problems, such as thermal expansion mismatch between the connector and the silicon wafer under test. Conventional structures, such as large area substrates having a large plurality of fanout traces which are electrically connected to pin or socket connectors, are typically implemented to manage connections between the IC under test, test electronics, and power management electronics.
The density of integrated circuits on semiconductor wafers continues to increase, due to semiconductor device scaling, with more gates and memory bits per unit area of silicon. As well, the use of larger semiconductor wafers (e.g. often having a nominal diameter of 8 inches or 12 inches) has become common. However, semiconductor test costs have increased on a cost per unit area of silicon basis. Therefore, semiconductor test costs have increased disproportionately over time, to become a greater percentage of the total manufacturing cost for each integrated circuit device.
Furthermore, advances in chip scale packaging (CSP) and other forms of small footprint packages have often made traditional packaged IC handlers obsolete for testing and burn-in.
In some conventional large surface area substrate integrated circuit (IC) test boards, electrical contacts between the test board and an integrated circuit wafer are typically provided by tungsten needle probes. However, tungsten needle probe technology is not able to meet the interconnect requirements of advanced semiconductors having higher pin counts, smaller pad pitches, and higher clock frequencies.
While emerging technologies have provided spring probes for different probing applications, most probes have inherent limitations, such as limited pitch, limited pin count, varying levels of flexibility, limited probe tip geometries, limitations of materials, and/or high costs of fabrication.
K. Banerji, A. Suppelsa, and W. Mullen III, Selectively Releasing Conductive Runner and Substrate Assembly Having Non-Planar Areas, U.S. Pat. No. 5,166,774 (24 Nov. 1992) disclose a runner and substrate assembly which comprises “a plurality of conductive runners adhered to a substrate, a portion of at least some of the conductive runners have non-planar areas with the substrate for selectively releasing the conductive runner from the substrate when subjected to a predetermined stress”.
A. Suppelsa, W. Mullen III and G. Urbish, Selectively Releasing Conductive Runner and Substrate Assembly, U.S. Pat. No. 5,280,139 (18 Jan. 1994) disclose a runner and substrate assembly which comprises “a plurality of conductive runners adhered to a substrate, a portion of at least some of the conductive runners have a lower adhesion to the substrate for selectively releasing the conductive runner from the substrate when subjected to a predetermined stress”.
D. Pedder, Bare Die Testing, U.S. Pat. No. 5,786,701 (28 Jul. 1998) disclose a testing apparatus for testing integrated circuits (ICs) at the bare die stage, which includes “a testing station at which microbumps of conductive material are located on interconnection trace terminations of a multilayer interconnection structure, these terminations being distributed in a pattern corresponding to the pattern of contact pads on the die to be tested. To facilitate testing of the die before separation from a wafer using the microbumps, the other connections provided to and from the interconnection structure have a low profile”.
D. Grabbe, I. Korsunsky and R. Ringler, Surface Mount Electrical Connector, U.S. Pat. No. 5,152,695 (06 Oct. 1992) disclose a connector for electrically connecting a circuit between electronic devices, in which “the connector includes a platform with cantilevered spring arms extending obliquely outwardly therefrom. The spring arms include raised contact surfaces and in one embodiment, the geometry of the arms provide compound wipe during deflection”.
H. Iwasaki, H. Matsunaga, and T. Ohkubo, Partly Replaceable Device for Testing a Multi-Contact Integrated Circuit Chip Package, U.S. Pat. No. 5,847,572 (08 Dec. 1998) disclose “a test device for testing an integrated circuit (IC) chip having side edge portions each provided with a set of lead pins. The test device comprises a socket base, contact units each including a contact support member and socket contact numbers, and anisotropic conductive sheet assemblies each including an elastic insulation sheet and conductive members. The anisotropic conductive sheet assemblies are arranged to hold each conductive member in contact with one of the socket contact members of the contact units. The test device further comprises a contact retainer detachably mounted on the socket base to bring the socket contact members into contact with the anisotropic sheet assemblies to establish electrical communication between the socket contact members and the conductive members of the anisotropic conductive sheet assemblies. Each of the contact units can be replaced by a new contact unit if the socket contact members partly become fatigued, thereby making it possible to facilitate the maintenance of the test device. Furthermore, the lead pins of the IC chip can be electrically connected to a test circuit board with the shortest paths formed by part of the socket contact members and the conductive members of the anisotropic conductive sheet assemblies”.
W. Berg, Method of Mounting a Substrate Structure to a Circuit Board, U.S. Pat. No. 4,758,927 (19 Jul. 1988) discloses “a substrate structure having contact pads is mounted to a circuit board which. has pads of conductive material exposed at one main face of the board and has registration features which are in predetermined positions relative to the contact pads of the circuit board. The substrate structure is provided with leads which are electrically connected to the contact pads of the substrate structure and project from the substrate structure in cantilever fashion. A registration element has a plate portion and also has registration features which are distributed about the plate portion and are engageable with the registration features of the circuit board, and when so engaged, maintain the registration element against movement parallel to the general plane of the circuit board. The substrate structure is attached to the plate portion of the registration element so that the leads are in predetermined position relative to the registration features of the circuit board, and in this position of the regi
Chong Fu Chiung
Mok Sammy
Clark Jasmine
Glenn Michael A.
Glenn Patent Group
NanoNexus, Inc.
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