Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Timing
Reexamination Certificate
2007-04-03
2007-04-03
Rodriguez, Paul (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Timing
C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C703S014000
Reexamination Certificate
active
10032208
ABSTRACT:
There is disclosed an IC simulation system operable to (i) store a plurality of HDL modules, each of which is representative of a circuit element, (ii) receive a HDL description of a desired circuit, and (iii) synthesize a circuit netlist as a function of the received HDL circuit description and ones of the plurality of HDL modules, the circuit netlist is responsible for defining behavioral relationships among associated ones of the HDL modules, and associate a timing-violation controller with the circuit netlist to ignore selected timing violations sensed as a function of various ones of the behavioral relationships during simulation of the desired circuit.
REFERENCES:
patent: 5696771 (1997-12-01), Beausang et al.
patent: 5841663 (1998-11-01), Sharma et al.
patent: 5907695 (1999-05-01), Dearth
National Semiconductor Corporation
Rodriguez Paul
Stevens Tom
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