Systems for implementing SDRAM controllers, and buses...

Details Systems for implementing SDRAM controllers, and buses... Systems for implementing SDRAM controllers, and buses...

2010-08-27

2011-10-25

Tseng, Cheng-Yuan (Department: 2184)

Electrical computers and digital data processing systems: input/

Input/output data processing

Data transfer specifying

C710S032000, C710S036000

Reexamination Certificate

active

08046505

ABSTRACT:
A memory controller including an address incrementer and a page crossing detect logic. The address incrementer may be configured to generate a next address in a burst from a current address in the burst. The page crossing detect logic may be configured to determine whether the burst will cross a memory page boundary based on the current address and the next address. The memory controller may be configured to automatically split bursts crossing page boundaries.

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