Systems for efficient retrieval from tiled memory surface to...

Computer graphics processing and selective visual display system – Computer graphics display memory system – Addressing

Reexamination Certificate

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C711S153000, C711S209000

Reexamination Certificate

active

07986327

ABSTRACT:
Embodiments of the present invention set forth a technique for optimizing the on-chip data path between a memory controller and a display controller within a graphics processing unit (GPU). A row selection field and a sector mask are included within a memory access command transmitted from the display controller to the memory controller indicating which row of data is being requested from memory. The memory controller responds to the memory access command by returning only the row of data corresponding to the requested row to the display controller over the on-chip data path. Any extraneous data received by the memory controller in the process of accessing the specifically requested row of data is stripped out and not transmitted back to the display controller. One advantage of the present invention is that the width of the on-chip data path can be reduced by a factor of two or more as a result of the greater operational efficiency gained by stripping out extraneous data before transmitting the data to the display controller.

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patent: 6104417 (2000-08-01), Nielsen et al.
patent: 6487575 (2002-11-01), Oberman
patent: 2003/0169265 (2003-09-01), Emberling
patent: 2005/0237329 (2005-10-01), Rubinstein et al.
patent: 2006/0129786 (2006-06-01), Yamazaki
Final Office Action, U.S. Appl. No. 11/555,628, dated Aug. 13, 2009.
Office Action, U.S. Appl. No. 11/555,628, mailed Nov. 30, 2009.

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