Systems and processes for asymmetrically shrinking a VLSI...

Details Systems and processes for asymmetrically shrinking a VLSI... Systems and processes for asymmetrically shrinking a VLSI...

2006-05-30

2006-05-30

Lin, Sun James (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07055114

ABSTRACT:
Processes, software and systems asymmetrically shrink a layout for a VLSI circuit design. A first VLSI circuit design layout, defined by a first fabrication process with first design rules, is asymmetrically scaled to a second VLSI circuit design layout defined by a second fabrication process with second design rules. Layouts of one or more leaf cells of the second VLSI circuit design layout are processed to ensure conformity to the second design rules.

REFERENCES:
patent: 5612893 (1997-03-01), Hao et al.
patent: 5936868 (1999-08-01), Hall
patent: 6699627 (2004-03-01), Smith et al.
patent: 6756242 (2004-06-01), Regan

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