Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-05-13
2004-07-27
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C714S030000, C714S724000, C324S763010, C324S764010, C324S765010
Reexamination Certificate
active
06769101
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally related to computer-aided circuit analysis and, more particularly, to systems and methods for partitioning chip designs into smaller blocks in order to test speed paths.
2. Discussion of the Related Art
Integrated circuits (ICs) are electrical circuits comprised of transistors, resistors, capacitors, and other components on a single semiconductor “chip” in which the components are interconnected to perform a variety of functions. Typical examples of ICs include, microprocessors, programmable logic devices (PLDs), electrically erasable programmable read only memory devices (EEPROMs), random access memory devices (RAMs), operational amplifiers and voltage regulators. A circuit designer typically designs the IC by creating a circuit schematic indicating the electrical components and their interconnections. Often, designs are simulated by computer to verify functionality and to ensure that performance goals are satisfied.
In electrical device engineering, the design and analysis work involved in producing electronic devices is often performed using electronic computer-aided design (E-CAD) tools. Electronic devices include analog, digital, mixed hardware, optical, electromechanical, and a variety of other electrical devices. In particular, circuit, very large scale integration chip, or other electrical device via E-CAD tools allows a curcuit to be thoroughly tested and often eliminates the need for building a prototype. Thus, today's sophisticated E-CAD tools may enable the circuit manufacturer to go directly to the manufacturing stage without having to perform costly, time consuming prototyping.
In order to perform the simulation and analysis of a hardware device, E-CAD tools utilize an electronic representation of the hardware device. A “netlist” is one common representation of a hardware device that includes the circuit. A “netlist” is a detailed circuit specification used by logic synthesizers, circuit simulators and other circuit design optimization tools. A netlist typically comprises a list of circuit components and the interconnections between those components.
The two forms of a netlist are the flat netlist and the hierarchical netlist. Often, a netlist will contain a number of circuit “modules” which are used repetitively throughout the larger circuit. A flat netlist will contain multiple copies of the circuit modules essentially containing no boundary differentiation between the circuit modules and other components in the device. By way of analogy, one graphical representation of a flat netlist is simply the schematic of the circuit device.
In contrast, a hierarchical netlist will only maintain one copy of a circuit module, which may be used in multiple locations. By way of analogy, one graphical representation of a hierarchical netlist would show the basic and/or non-repetitive devices in schematic form and the more complex and/or repetitive circuit modules would be represented by “black boxes.” As will be appreciated by those skilled in the art, a black box is a system or component where the inputs, outputs, and general function are known, but the contents of which are not shown. These “black box” representations, hereinafter called “modules,” will mask the complexities therein, typically showing only input/output ports.
An IC design can be represented at different levels of abstraction, such as at the register-transfer level (RTL) and the at logic level, using a hardware description language (HDL). VHDL® and Verilog® are examples of HDL languages. At any abstraction level, an IC design is specified using behavioral or structural descriptions, or a mix of both. At the logic level, the behavioral description is specified using Boolean equations. The structural description is represented as a netlist of primitive cells. Examples of primitive cells are, among others, full-adders, logic gates, latches, and flip flops.
Set forth above is some very basic information regarding integrated circuits and other circuit schematics that are represented in netlists. Systems are presently known that use the information provided in netlists to evaluate circuit timing and other related parameters. More specifically, systems are known that perform a timing analysis of circuits using netlist files. Although the operational specifics may vary from system to system, generally, such systems operate by identifying certain critical timing paths, then evaluating the circuit to determine whether timing violations may occur through the critical paths. As is known, timing specifications may be provided to such systems by way of a configuration file.
While there is extensive testing of designs of electronic devices in the design phase, there is also a need for testing of electronic devices after manufacture to eliminate any devices with manufacturing flaws. Much of the same input information utilized in the testing of the virtual circuits may be utilized in the creation of tests for the actual hardware component. These data inputs can be utilized in test generation systems.
Test generation refers to the generation of vectors to test whether the actual device is defect free and meets the timing specifications it was designed to meet. Typically, test generation systems that generate test programs to test an actual device require significant amounts of run time and are memory intensive. This is because the test programs ordinarily generate tests for the entire chip at once.
Thus, a heretofore unaddressed need exists in the industry to address the aforementioned and/or other deficiencies and inadequacies as chip complexity and density increases.
SUMMARY OF THE INVENTION
The present invention provides chip analyzer systems and methods for partitioning chip designs into smaller blocks in order to test speed paths for an integrated circuit. Briefly described, in architecture, one embodiment of the system includes a chip analyzer and an automatic test generator. The chip analyzer partitions information corresponding to the integrated circuit into a plurality of circuit configuration blocks, and creates a model of a selected circuit configuration block in the integrated circuit. The automatic test generator receives the model from the chip analyzer, and creates tests from the model to determine the correctness of the integrated circuit.
The invention can also be viewed as providing one or more methods for partitioning of a chip design into smaller blocks in order to test speed paths more efficiently for an integrated circuit. In this regard, one such method can be summarized by the following steps: (1) partitioning the integrated circuit into a plurality of circuit configurations; (2) selecting a circuit configuration on the integrated circuit to be tested; (3) identifying logic driving input logic in the selected circuit configuration of the integrated circuit; and (4) identifying logic driving output logic in the selected circuit configuration of the integrated circuit.
REFERENCES:
patent: 5831992 (1998-11-01), Wu
patent: 6070261 (2000-05-01), Tamarapalli et al.
patent: 2002/0188432 (2002-12-01), Houlihane et al.
patent: 2003/0025519 (2003-02-01), Hsieh
patent: 2003/0110457 (2003-06-01), Nadeau-Dostie et al.
Arun Balakrishnan, “Peripheral Patititioning and Tree Decomposition for Partial Scan,” IEEE, 1997, pp. 181-186.*
Bayraktaroglu et al., “Diagnostis for Scan-Based BIST: Reaching Deep into the Signatures,” IEEE, 2001, pp. 102-109.
LandOfFree
Systems and methods providing scan-based delay test generation does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Systems and methods providing scan-based delay test generation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Systems and methods providing scan-based delay test generation will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3256159