Systems and methods for writing data with a FIFO interface

Details Systems and methods for writing data with a FIFO interface Systems and methods for writing data with a FIFO interface

2006-09-28

2008-09-16

Dang, Khanh (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C714S716000, C714S715000, C714S750000, C709S231000, C375S221000

Reexamination Certificate

active

07426599

ABSTRACT:
Application Specific Integrated Circuit (“ASIC”) devices, such as Field Programmable Gate Arrays (“FPGAs”), may be interconnected using serial I/O connections, such as high speed multi-gigabit serial transceiver (“MGT”) connections. For example, serial I/O connections may be employed to interconnect a pair of ASICs to create a high bandwidth, low signal count connection, and in a manner so that any given pair of multiple ASIC devices on a single circuit card may communicate with each other through no more than one serial data communication link connection step. A reconfigurable hardware architecture (“RHA”) may be configured to include a communications infrastructure that uses a high-bandwidth packet router to establish standard communications protocols between multiple interfaces and/or multiple devices that may be present on a single circuit card. Additionally, a communications infrastructure may be established across multiple circuit cards.

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