Systems and methods for wiring circuit components

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000

Reexamination Certificate

active

11107038

ABSTRACT:
Systems and methods for arranging parallel wires to reduce the capacitance variations. In one embodiment, multiple first components arranged as a linear array are coupled to a second component at the end of this linear array by corresponding signal wires. Each signal wire has a perpendicular portion extending perpendicular to the direction of the linear array, and a parallel portion which runs parallel to the direction of the linear array. The parallel portions are staggered so that longer ones of the parallel portions are adjacent to the shorter ones of the parallel portions, instead of simply being arranged from longest to shortest. In one embodiment, the longer half of the parallel portions decrease in length across the series of parallel portions, while the shorter half of the parallel portions increase in length. In another embodiment, successively longer/shorter parallel portions alternate sides of the series.

REFERENCES:
patent: 6505332 (2003-01-01), Oda
patent: 6643838 (2003-11-01), Rarick
patent: 7032205 (2006-04-01), Kato
patent: 2001/0004763 (2001-06-01), Kato
patent: 2005/0216876 (2005-09-01), Proebsting et al.
patent: PH07-153844 (1995-06-01), None
patent: PH10-308451 (1998-11-01), None

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