Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-06-26
2004-12-28
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06836874
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention generally relates to computer-aided integrated circuit design systems, and more particularly to systems and methods for accurately determining clock signal timing constraints when designing an integrated circuit.
2. Description of the Related Art
Integrated circuits are electrical circuits that arrange transistors, resistors, capacitors, and other components on a single semiconductor die or substrate, upon which the various components are interconnected to perform a variety of functions. Typical examples of integrated circuits include, for example, microprocessors, programmable-logic devices (PLDs), electrically-erasable-programmable-read-only memory devices (EEPROMs), random-access-memory (RAM) devices, operational amplifiers, voltage regulators, etc.
Often, circuit designs are simulated by computer to verify functionality and timing to ensure that performance goals will be satisfied. Design and circuit analysis procedures are often performed using electronic-computer-aided design (E-CAD) tools. The design and subsequent simulation of a printed circuit board, a very large scale integration (VLSI) circuit, or other electrical devices via E-CAD tools allows a product design to be confirmed and often eliminates the need for building a prototype. Thus, E-CAD tools may enable a VLSI circuit manufacturer to bypass costly and time consuming prototype construction and performance verification stages in the product development process.
A VLSI circuit design can be represented at different levels of abstraction using a hardware description language. Some hardware description languages support circuit description at a register-transfer level, as well as at a logic level.
At any abstraction level, a circuit design may be specified using behavioral or structural descriptions or a combination of both. A behavioral description is often specified using Boolean functions. A structural description may include a list describing the various connections in a network of primitive or higher-level cells. Such a list is often called a “netlist.” The netlist may be used by logic synthesizers, circuit simulators, and other circuit design optimization tools to model the circuit. Examples of primitive cells are, among others, full-adders, logic gates, latches, and flip-flops. A register is an example of a higher-level (i.e., a non-primitive) cell.
A number of known systems use information provided in netlists to evaluate circuit timing and other related parameters. Although the operational specifics vary from system to system, generally such systems operate by identifying certain critical timing paths, modeling the conductors and the various cells defining each critical timing path using a resistor-capacitor (RC) network, and then evaluating the circuit to determine whether timing violations occur for signals required to traverse each of the critical paths. Static timing tools, a specific type of optimization tool, are used to confirm that received input signals will arrive in time for the receiving block to process the signals, and block output signals will reach their designated destination circuits before the next clock cycle. Static timing tools are designed with a focus on cell to cell (e.g., register to register) travel time estimates.
Unfortunately, this cell to cell approach is not well suited to convey useful and accurate timing information in the early design stages of a VLSI circuit. First, VLSI circuits are commonly designed by circuit design teams. Each circuit designer or a team of circuit designers are assigned to create the circuits that will be used in one or more functional areas or blocks across the die that will contain the entire circuit. In the final product, each of the separately designed functional blocks must function correctly over time while receiving input signals and sending output signals across functional block interfaces. This functional block by functional block design approach can lead to circuit timing flaws that may not be identified until the functional blocks are integrated.
In addition, these block level interface-timing problems increase as a function of clock signal frequency. As the clock signal frequency increases, the corresponding shorter clock cycles increase the relative impact of signal transfer delays between an interface of a functional block and the various circuit components (e.g., registers) contained within respective blocks. Thus, static timing tools, designed with the intention of confirming a circuit design, are not suited to generate timing information that can be communicated to the designers of each of the functional blocks before they finalize the details of their assigned block circuit designs. Moreover, timing tools do not provide a mechanism to convey block level to block level timing information for a multi-level integrated circuit design.
In light of competitive pressures to design functional VLSI circuits with confidence that functional blocks will operate as desired over time, while reducing the design life cycle and development costs, it can be understood that there is a need for systems and methods that address these and/or other shortcomings of the prior art, while providing a functional VLSI circuit design.
SUMMARY OF THE INVENTION
Systems and methods of the present invention relate to time budgeting the various functional blocks of an integrated circuit during circuit design. A time budget is a schedule that defines signal-timing relationships between various signal paths across an integrated circuit. The systems methods of the present invention can be applied to generate timing constraints at multiple levels of circuit abstraction. The systems and methods account for signal propagation delays between functional block interfaces including delays between hierarchically associated functional blocks. More specifically, the systems and methods of the present invention generate accurate timing constraints that may be used by circuit designers tasked with developing the various circuits within a functional block.
A representative system includes an information acquisition device, a computer, and a memory element associated with the computer, the memory element configured to store information used to describe a functional block and associate a timing point that accounts for signal delays between the border of the functional block and the various circuit elements within the block.
A representative method includes the following steps: acquiring circuit information that describes the conductors that traverse a border of the functional block, inserting a timing point in the information, determining a delay time in response to the timing point, and deriving a constraint in response to the delay time.
Other systems, methods, and features of the present invention will be or become apparent to one skilled in the art upon examination of the following drawings and detailed description. It is intended that all such additional systems, methods, and features are included within this description, are within the scope of the present invention, and are protected by the accompanying claims.
REFERENCES:
patent: 5859776 (1999-01-01), Sato et al.
patent: 6230304 (2001-05-01), Groeneveld et al.
patent: 6496962 (2002-12-01), Dalton
patent: 2002/0124230 (2002-09-01), Cai et al.
patent: 2003/0014720 (2003-01-01), Ito et al.
patent: 2003/0121013 (2003-06-01), Moon et al.
Batchelor Dennis B.
Mielke David James
Agilent Technologie,s Inc.
Siek Vuthe
Tat Binh
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