Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2001-03-27
2004-06-15
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S733000, C365S201000
Reexamination Certificate
active
06751762
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates generally to systems and methods for testing a memory and, more particularly, to systems and methods for testing a memory by compressing in a time direction using a built-in self tester (BIST).
2. Description of the Related Art
Typically, compression of data using the built-in self tester (BIST) and other techniques is by I/O compression, because integrated circuits designs require testing following their development, for purposes of detecting faults.
A typical method of testing, referred to as a built-in self testing (BIST) has been used with components such as programmable logic arrays (PLAs). Using this approach, the logic required to test for the circuit, and the logic required before analysis of the circuit relative to these tests, are obtained with hardware placed in the same system as the circuit under test. Consequently, the circuit is capable of testing itself and reporting to its environment whether it is a working circuit or not. The components tested include cards, wafers, or an integrated circuit chip, which may include a memory.
When testing components, on-chip testing is best, and it is feasible to test all storage points in the logical “0” and “1” states.
When automated built-in self testing (ABIST) of memories is used, an interface to the memory through input and output boundry latches is required. These latches function as logic gate storage elements. Each input and output has a latch through which ABIST test data is supplied and captured for compression. Data sent through the input latches is “muxed” i.e., multiplexed with functional data and output to the memory input. The mux selection between the test data and the functional data is controlled by a tester machine.
The latch inputs are provided off of the memory outputs to observe the data i.e. provided to the testing structure in parallel to other logic circuitry on the chip. Each of the latches feeds directly to the compression circuits. The data is then compared to expected data and compressed to generate a single fail signature, whereupon the single fail signature is output off-chip for analysis and evaluation.
U.S. Pat. No. 5,954,830 disclose a memory test apparatus for use with memory having a plurality of outputs, including a built-in, self-testing (BIST) test state machine having a plurality of address outputs; a plurality of multiplexers controlled by the address outputs of the test state machines; and means for testing the plurality of outputs of the memory based on the address outputs of the test state machine, wherein the plurality of outputs of the memory are input to the plurality of multiplexers and a number of outputs tested simultaneously is less than a total number of outputs of the memory.
An array of built-in self test (ABIST)is disclosed in U.S. Pat. No. 5,859,804. In this ABIST, a system control circuit provides per address read/write commands to an array A, controls address stepping, influences data pattern generation to the array and to a data compression circuit, and controls results logging in the two dimension failed address register. During the reading operation, expected data from a data pattern generator is applied to the data compression circuit for data output evaluation.
U.S. Pat. No. 5,553,082 disclose a built-in self-test (BIST) for comparator logic circuitry at the output of a memory array output. Output from compression/compare circuit
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is a real-time “pass/fail” signal which may be monitored for detection of a memory array failure.
A method for testing field programmable gate arrays (FPGA's) is disclosed in U.S. Pat. No. 6,003,150. The method is for diagnostic testing of field programmable gate arrays (FPGA's). In particular, the testing method is adapted to perform output response analysis by means of direct comparison.
U.S. Pat. No. 5,912,901 disclose a built-in self-test apparatus and method for testing integrated circuits which capture failure information for a selected failure. The BIST apparatus comprises a clock generator, which generates at least a first clock signal, and a built-in self-tester, which applies predetermined input data patterns to the integrated circuit in response to the first clock signal.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide improved systems and methods of testing a memory.
To achieve this and other objects of the present invention, there is a method of testing a memory in an integrated circuit (IC) The method comprises the steps, performed in the integrated circuit, of sending a first value to a plurality of locations; initializing a state; subsequently, performing the following steps multiple times: changing a column address associated with a data line; and reading from the data line, comparing the read value to the first value, and setting the state to a value depending on the results of the comparing and the current value of the state.
According to yet another aspect of the present invention, an integrated circuit (IC) comprises a plurality of addressable locations; a data line selectively responsive to one of multiple ones of the addressable locations; a first element that stores a state; first circuitry, activatable multiple times after initialization of the element, that reads from the data line, compares the read value to a first value, and selectively modifies the state to a value depending on the results of the comparing and the current value of the state.
According to yet another aspect of the present invention, a system comprises means for sending a first value to a plurality of locations; means for initializing a state; means for changing a column address associated with a data line; and means for reading from the data line, comparing the read value to the first value, and setting the state to a value depending on the results of the comparing and the current value of the state.
REFERENCES:
patent: 5553082 (1996-09-01), Connor et al.
patent: 5859804 (1999-01-01), Hedberg et al.
patent: 5912901 (1999-06-01), Adams et al.
patent: 5954830 (1999-09-01), Ternullo, Jr.
patent: 6003150 (1999-12-01), Stroud et al.
patent: 6304989 (2001-10-01), Kraus et al.
Gandhi Dipakkumar
Infineon - Technologies AG
Slater & Matsil L.L.P.
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