Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2011-06-07
2011-06-07
Barnie, Rexford N (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S159000
Reexamination Certificate
active
07956790
ABSTRACT:
Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a retimed analog to digital converter is disclosed that includes a first set of sub-level interleaves and a second set of sub-level interleaves. The first set of sub-level interleaves includes a first sub-level interleave with a first set of comparators synchronized to a first clock phase, and a second sub-level interleave with a second set of comparators synchronized to a second clock phase. The second set of sub-level interleaves includes a third sub-level interleave with a third set of comparators synchronized to a third clock phase, and a fourth sub-level interleave with a fourth set of comparators synchronized to a fourth clock phase. A global interleave selects one of the first set of comparators based at least in part on an output from the second set of sub-level interleaves, and one of the third set of comparators based at least in part on an output from the first set of sub-level interleaves. In some instances of the aforementioned embodiments, an output of the first sub-level interleave and an output of the second sub-level interleave are synchronized to the third clock phase, and an output of the third sub-level interleave and an output of the fourth sub-level interleave are synchronized to the first clock phase.
REFERENCES:
patent: 4672518 (1987-06-01), Murdock
patent: 4686617 (1987-08-01), Colton
patent: 4837495 (1989-06-01), Zansky
patent: 4885674 (1989-12-01), Varga et al.
patent: 4912470 (1990-03-01), Hosotani et al.
patent: 4918450 (1990-04-01), Sugiyama et al.
patent: 5072221 (1991-12-01), Schmidt
patent: 5173698 (1992-12-01), Gulczynski
patent: 5182477 (1993-01-01), Yamasaki et al.
patent: 5225837 (1993-07-01), Hosotani et al.
patent: 5272701 (1993-12-01), Tsuruoka
patent: 5296856 (1994-03-01), Mantong
patent: 5418493 (1995-05-01), Dijkmans
patent: 5510745 (1996-04-01), Hamano et al.
patent: 5689178 (1997-11-01), Otake
patent: 5734297 (1998-03-01), Huijsing et al.
patent: 5789973 (1998-08-01), Barrett et al.
patent: 5801564 (1998-09-01), Gasparik
patent: 5809060 (1998-09-01), Cafarella et al.
patent: 5861829 (1999-01-01), Sutardja
patent: 5874911 (1999-02-01), Kodama
patent: 5929705 (1999-07-01), Zhang et al.
patent: 5936466 (1999-08-01), Andoh et al.
patent: 6002356 (1999-12-01), Cooper
patent: 6011502 (2000-01-01), Kao
patent: 6081219 (2000-06-01), Prasanna
patent: 6111467 (2000-08-01), Luo
patent: 6181269 (2001-01-01), Nishiuchi et al.
patent: 6225859 (2001-05-01), Irvine et al.
patent: 6232908 (2001-05-01), Nakaigawa
patent: 6369743 (2002-04-01), Ono
patent: 6373423 (2002-04-01), Knudsen
patent: 6404372 (2002-06-01), Heithoff
patent: 6404374 (2002-06-01), Yu et al.
patent: 6556081 (2003-04-01), Muza
patent: 6556158 (2003-04-01), Steensgaard-Madsen
patent: 6563445 (2003-05-01), Sabouri
patent: 6580382 (2003-06-01), Yung
patent: 6600373 (2003-07-01), Bailey et al.
patent: 6605993 (2003-08-01), Suzuki
patent: 6653966 (2003-11-01), van der Goes et al.
patent: 6717945 (2004-04-01), Jue et al.
patent: 6744432 (2004-06-01), Morein
patent: 6756841 (2004-06-01), Jaussi et al.
patent: 6784824 (2004-08-01), Quinn
patent: 6816101 (2004-11-01), Hietala et al.
patent: 6922083 (2005-07-01), Tanaka et al.
patent: 6956517 (2005-10-01), Baker et al.
patent: 7002504 (2006-02-01), McMahill
patent: 7019507 (2006-03-01), Dittmer et al.
patent: 7116260 (2006-10-01), Luh
patent: 7129874 (2006-10-01), Bjornsen
patent: 7190298 (2007-03-01), Mulder
patent: 7209068 (2007-04-01), Chen et al.
patent: 7233277 (2007-06-01), Roh
patent: 7262724 (2007-08-01), Hughes et al.
patent: 7333580 (2008-02-01), Parhi
patent: 7362153 (2008-04-01), Sumesaglam
patent: 7471228 (2008-12-01), Cho et al.
patent: 7482844 (2009-01-01), Brady et al.
patent: 7696915 (2010-04-01), Chmelar et al.
patent: 2002/0186776 (2002-12-01), Cosand
patent: 2005/0151588 (2005-07-01), Bailey et al.
patent: 2006/0071709 (2006-04-01), Maloberti et al.
patent: 2006/0132242 (2006-06-01), Han et al.
patent: 2007/0183006 (2007-08-01), Lee
patent: 2008/0048896 (2008-02-01), Parthasarthy et al.
U.S. Appl. No. 12/024,893, filed Feb. 1, 2008, Bailey.
U.S. Appl. No. 12/024,909, filed Feb. 1, 2008, Bailey.
U.S. Appl. No. 12/025,897, filed Nov. 20, 2007, Bailey et al.
U.S. Appl. No. 12/025,914, filed Nov. 20, 2007, Bailey et al.
U.S. Appl. 12/134,488, filed Jun. 6, 2008, Chmelar.
U.S. Appl. 12/134,501, filed Jun. 6, 2008, Chmelar.
U.S. Appl. 12/134,523, filed Jun. 6, 2008, Chmelar.
Brandt et al., “A 75-mW, 10-b, 10 MSPS CMOS Subranging ADC with 9.5 Effective Bits at Nyquist”, IEEE J. Solid State Circuits, vol. 34, No. 12, pp. 1788-1795, Dec. 1999.
Diato et al., “A 14-bit 20-MS/s Pipelined ADC With Digital Distortion Calibration,” IEEE J. Solid-State Circuits, vol. 41, No. 11, pp. 2417-2423. Nov. 2006.
Gupta, et al., “A 1 GS/s 11 b Time Interleaved ADC in 0.13um CMOS”, ISSCC Dig. Tech. Papers, pp. 576-577, Feb 2006.
Katsuria, S. et al., “Techniques for High-Speed Implementationof Nonlinear Cancellation”, IEEE Joun. Communications, vol. 9, No. 5, Jun. 1991, pp. 711-717.
Kim et al., “A 10-b, 10MS/s CMOS A/D Converter”, IEEE J. Solid State Circuits, vol. 32, No. 3, pp. 302-311, Mar. 1997.
Mangelsdorf, C.W., “A 400-MHz Input Flash Converter With Error Correction”, IEEE Journal of Solid-State Circuits, pp. 184-191, Feb 1990, vol. 25 Issue 1.
Mehr, et al., “A 55-mW, 10-bit, 40-Msample/s Nyquist-Rate CMOS ADC,” IEEE J. Solid-State Circuits, vol. 35, No. 3, pp. 302-311, Mar. 2000.
Nagaraj et al., “A 250 mW 8-b, 52 Msamples/s Parallel-Pipelined A/D Converter with Reduced Number of Amplifiers”, IEEE J. Solid State Circuits, vol. 32, pp. 312-320, Mar. 1997.
Schinkel, Daniel et al. A double-Tail Latch-Type Voltage Sense Maplifier with 18ps Setup+Hold Time, Feb. 13, 2007, ISSCC 2007, Session 13, pp. 314-15 and 605 IEEE.
Schmid & Moschtz, “A Tunable, Video-Frequency, Low Power Single Amplifier Biquadratic Filter in CMOS”, Circuits and Systems, 1999, ISCAS'99. IEEE Int. Sym. on vol. 2, May 2.
Sedra, Adel S. et al. “Optimum Configurations for Single-Amplifier Biquadratic Filters” Dec. 1980, IEEE Trans. On Cir. and Sys., vol. CAS-27, No. 12, pp. 1155-1163.
Singer et al., “A 14-bit 10-MHz Calibrations-Free CMOS Pipelined A/D Converter,” in Symp. VLSI Circuits Dig. Tech Papers, Jun. 1996, pp. 38-39.
U.S. Appl. No. 12/669,482, filed Jun. 6, 2008, Chmelar.
Chmelar Erik
Ito Choshu
Loh William
Barnie Rexford N
Hamilton, DeSanctis & Cha (LSI)
Lauture Joseph
LSI Corporation
LandOfFree
Systems and methods for synchronous, retimed analog to... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Systems and methods for synchronous, retimed analog to..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Systems and methods for synchronous, retimed analog to... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2681099